Browsing by Author "Lin, Chia-Sheng"

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Analysis of Anomalous Capacitance Induced by TAGIDL in p-Channel LTPS TFTs
(2010)
Lin, Chia-Sheng
;
Chen, Ying-Chung
;
Chang, Ting-Chang
;
Li, Hung-Wei
;
Chen, Shih-Ching
In this work, a mechanism of anomalous capacitance in p-channel low temperature polycrystalline silicon thin film transistors (LTPS TFTs) was investigated. In general, the effective capacitance of the LTPS TFTs was only dependent with the overlap area between the gate and source/drain under the off-state. However, the experimental results reveal that the off-state capacitance was increased with decreasing measurement frequency and/or with increasing measurement temperature. By fitting the curve of the drain current vs electric field under off-state region, it was verified that the trap-assisted gate-induced drain leakage (TAGIDL) consists of the Pool-Frenkel emission and thermal field emission. In addition, the charge density calculated from the C(gsd)-V(g) measurement also has the same dependence with electric field. This result demonstrates that the anomalous capacitance is mainly due to the TAGIDL. To suppress the anomalous capacitance, a band-to-band hot electron stress was utilized to reduce the vertical electric field between the gate and the drain. The electric field simulation was also performed by TCAD software. (C) 2010 The Electrochemical Society. [DOI: 10.1149/1.3483759] All rights reserved.
Analysis of Degradation Mechanism in SONOS-TFT Under Hot-Carrier Operation
(2010-12-01)
Chen, Te-Chih
;
Chang, Ting-Chang
;
Chen, Shih-Ching
;
Hsieh, Tien-Yu
;
Jian, Fu-Yen
This letter investigates the degradation mechanism of polycrystalline silicon thin-film transistors with a silicon-oxide-nitride-oxide-silicon structure under OFF-state stress. During the electrical stress, the hot hole generated from band-to-band tunneling process will inject into gate dielectric, and the significant ON-state degradation (more than 1 order) indicates that the interface states are accompanied with hot-hole injection. In addition, the asymmetric I-V characteristics indicate that the interface states are located near the drain side. Moreover, the ISE-TCAD simulation tool was utilized to model the degradation mechanism and analyze trap states distribution. Although both the vertical and lateral electrical fields are factors for degradation and hot-hole injection, the degradation is mainly affected by the lateral electrical field over a critical point.
Anomalous Capacitance Induced by GIDL in P-Channel LTPS TFTs
(2009-11-01)
Lin, Chia-Sheng
;
Chen, Ying-Chung
;
Chang, Ting-Chang
;
Chen, Shih-Ching
;
Jian, Fu-Yen
In this letter, a mechanism of anomalous capacitance in p-channel low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs) was investigated. In general, the effective capacitance was only the overlap region and independent with the frequency in LTPS TFTs under the OFF state. However, our experimental results reveal that the capacitance was related with the leakage current and that it was dependent with the measurement frequencies when operated at the OFF-state region. The increase of the capacitance value is verified to be due to the increase of the electron capacitance originating from a gate-induced drain-leakage (GIDL) one. Nevertheless, the GIDL-induced electron capacitance can be suppressed by employing band-to-band hot electron stress.
Anomalous on-current and subthreshold swing improvement in low-temperature polycrystalline-silicon thin-film transistors under Gate bias stress
(2011-03-21)
Lin, Chia-Sheng
;
Chen, Ying-Chung
;
Chang, Ting-Chang
;
Jian, Fu-Yen
;
Li, Hung-Wei
This work investigates an improvement in anomalous on-current and subthreshold swing (SS) in Low-temperature polycrystalline-silicon thin-film transistors after positive gate bias stress. The experimental results reveal that the improved electric properties are due to the hole trapping at SiO(2) above the lightly doped drain regions, which causes a strong electric field at the gate corners. The effect of the hole trapping is to reduce the effective channel length and the SS. Besides, the stress-related electric field was also simulated by TCAD software to verify the mechanism above. (C) 2011 American Institute of Physics. [doi:10.1063/1.3568895]
Charge-Trapping-Induced Parasitic Capacitance and Resistance in SONOS TFTs Under Gate Bias Stress
(2011-03-01)
Lin, Chia-Sheng
;
Chen, Ying-Chung
;
Chang, Ting-Chang
;
Jian, Fu-Yen
;
Li, Hung-Wei
This letter investigates the charge-trapping-induced parasitic resistance and capacitance in silicon-oxide-nitride-oxide-silicon thin-film transistors under positive and negative dc bias stresses. The results identify a parasitic capacitance in OFF-state C-V curve caused by electrons trapped in the gate insulator near the defined gate region during the positive stress, as well as the depletion induced by those trapped electrons. Meanwhile, the induced depletions in source/drain also degraded the I-V characteristic when the gate bias is larger than the threshold voltage. However, these degradations slightly recover when the trapped electrons are removed after negative bias stress. The electric field in the undefined gate region is also verified by TCAD simulation software.
Degradation of Low Temperature Polycrystalline Silicon Thin Film Transistors under Negative Bias Temperature Instability Stress with Illumination Effect
(2010)
Lin, Chia-Sheng
;
Chen, Ying-Chung
;
Chang, Ting-Chang
;
Li, Hung-Wei
;
Hsu, Wei-Che
This work investigates negative bias temperature instability (NBTI) in low temperature polycrystalline silicon thin film transistors (LTPS TFTs) in a darkened and in an illuminated environment of different light intensities. Experimental results reveal that the generations of interface state density (N(it)) are identical under various illuminated intensity NBTI stresses. Nevertheless, the degradation of the grain boundary trap (N(trap)) under illumination was more significant than that for the darkened environment, with degradation increasing as illumination intensity increases. This phenomenon is mainly caused by the extra number of holes generated during the illuminated NBTI stress. The increased N(trap) degradation leads to an increase in the darkened environment leakage current. This indicates that more traps are generated in the drain junction region than from carrier tunneling via the trap, resulting in leakage current. Conversely, an increase in N(trap) degradation results in a decrease in the photoleakage current. This indicates that the number of recombination centers increases in the poly-Si bulk, affecting photosensitivity in LTPS TFTs.
Effect of Lateral Body Terminal on Silicon-Oxide-Nitride-Oxide-Silicon Thin-Film Transistors
(2011-10-01)
Li, Hung-Wei
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Chang, Ting-Chang
;
Chang, Geng-Wei
;
Lin, Chia-Sheng
;
Tsai, Tsung-Ming
We investigate lateral-body-terminal silicon-oxide-nitride-oxide-silicon thin-film transistors (LBT SONOS TFTs) under erasing operation. These devices have superior erasing efficiency by gate as well as lateral body electrode exerting bias. The erasing mechanism of LBT SONOS TFTs has been illustrated by the energy band diagrams. Holes gain sufficient energy by the electric field in the deep-depletion region to surmount the tunneling oxide barrier because of exerting body bias under erasing operation. In addition, the lateral body terminal exerting bias can enhance the erasing efficiency and is confirmed by different erasing conditions and structures. In addition, to verify the hole current injecting from the lateral body site, the size effect of LBT SONOS TFTs is also discussed.
Enhanced reactivity of metal/metal oxide-porous carbon nanocomposites for electrochemical and photocatalytic applications
(2016-08-20)
Doong, Ruey-An
;
Lin, Chia-Sheng
;
Bindumadhavan, Kartick
;
環境工程研究所
;
Institute of Environmental Engineering
Illumination-Assisted Negative Bias Temperature Instability Degradation in Low Temperature Polycrystalline Silicon Thin-Film Transistors
(2009)
Lin, Chia-Sheng
;
Chen, Ying-Chung
;
Chang, Ting-Chang
;
Hsu, Wei-Che
;
Chen, Shih-Ching
In this work, the negative bias temperature instability (NBTI) in low temperature polycrystalline silicon thin-film transistors in a darkened and in an illuminated environment was investigated. Experimental results reveal that the generation of interface state density (N(it)) showed no change between the different NBTI stresses. Nevertheless, the degradation of the grain boundary trap (N(trap)) under illumination was more significant than that in the darkened environment. This phenomenon is mainly caused by the extra number of holes generated during the illuminated NBTI stress.
Investigating the degradation behavior caused by charge trapping effect under DC and AC gate-bias stress for InGaZnO thin film transistor
(2011-07-11)
Chen, Te-Chih
;
Chang, Ting-Chang
;
Hsieh, Tien-Yu
;
Lu, Wei-Siang
;
Jian, Fu-Yen
This letter investigates the degradation mechanism of amorphous indium-gallium-zinc oxide thin-film transistors under gate-bias stress. The larger V(t) shift under positive AC gate-bias stress when compared to DC operation indicates that an extra electron trapping mechanism occurs during rising/falling time during the AC pulse period. In contrast, the degradation behavior under illuminated negative gate-bias stress exhibits the opposite degradation tendency. Since electron and hole trapping are the dominant degradation mechanisms under positive and illuminated negative gate-bias stress, respectively, the different degradation tendencies under AC/DC operation can be attributed to the different trapping efficiency of electrons and holes. (C) 2011 American Institute of Physics. [doi: 10.1063/1.3609873]
Investigation of gate-bias stress and hot-carrier stress-induced instability of InGaZnO thin-film transistors under different environments
(2013-09-01)
Hsieh, Tien-Yu
;
Chang, Ting-Chang
;
Chen, Te-Chih
;
Tsai, Ming-Yen
;
Chen, Yu-Te
This paper investigates the temperature and ambiance effects on various reliability issues for InGaZnO thin film transistors with an organic passivation layer. Hot-carrier stress and gate-bias stress are carried out under different environmental temperatures and ambient gases. The device exhibits relatively good stability under room temperture, whereas high temperature enhances degradation. Futhermore, different degradation behaviors after gate-bias stress in atmosphere and in vacuum can be attributed to gas adsorption/desorption-induced instability. Moreover, capacitance-voltage measurement techinique is utilized to analyze the degradation mechanism and to extract the density of state (DOS). The result reveals that the threshold voltage shift after both hot-carrier and gate-bias stress originates from the charge-trapping effect at the interface of gate insulator and active layer, with the extra trap states generated during stress responsible for C-V curve distortion. In addition, the asymmetric degradation behavior of gate-to-drain capacitance (Cgd) and gate-to-source capacitance (Cgs) indicates that trap states are generated near the drain side. (C) 2012 Elsevier B.V. All rights reserved.
NBTI Degradation in LTPS TFTs Under Mechanical Tensile Strain
(2011-07-01)
Lin, Chia-Sheng
;
Chen, Ying-Chung
;
Chang, Ting-Chang
;
Jian, Fu-Yen
;
Hsu, Wei-Che
This letter investigates the negative-bias temperature instability (NBTI) degradation of p-channel low-temperature polycrystalline-silicon thin-film transistors (LTPS TFTs) under mechanical tensile stress. Experimental results reveal that the interface state density N(it) and grain boundary trap density N(trap) of tensile-strained LTPS TFTs are more pronounced than those of unstrained LTPS TFTs. Extracted density of states and conduction activation energy E(a) both show increases due to the strained Si-Si bonds, which implies that strained Si-Si bonds are able to react with dissociated H during NBTI stress. Therefore, NBTI degradation is more significant after tensile strain than in an unstrained condition.
Oxygen-Adsorption-Induced Anomalous Capacitance Degradation in Amorphous Indium-Gallium-Zinc-Oxide Thin-Film-Transistors under Hot-Carrier Stress
(2012)
Chung, Wan-Fang
;
Chang, Ting-Chang
;
Lin, Chia-Sheng
;
Tu, Kuan-Jen
;
Li, Hung-Wei
This paper investigates anomalous capacitance-voltage (C-V) degradation in amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film-transistors (TFTs) under hot carrier stress. In vacuum hot carrier stress, both the gate-to-drain capacitance (C(GD)) and the gate-to-source capacitance (C(GS)) curves exhibited positive shifts due to electron trapping in the gate dielectric. In addition, an observed increase in capacitance value at a lower gate voltage in the C(GD) measurement only can be ascribed to interface state creation. However, when the hot carrier stress was performed in an oxygen-rich environment, the C(GD)-V(G) curve showed a significantly positive shift due to the electric-field-induced oxygen adsorption near the drain terminal. The degradation in the C(GS)-V(G) curve is due not only to the positive shift, but also the anomalous two step turn-on behavior. This phenomenon can be ascribed to the electron trapping in the gate dielectric and electric-field-induced oxygen adsorption on the channel layer, especially in the area adjacent to the drain terminal. The electron trapping increased the source energy barrier, with the electric-field-induced oxygen adsorption further raising the energy-band near the drain, resulting in a two-step turn-on behavior in the C(GS)-V(G) curve. (C) 2012 The Electrochemical Society. [DOI: 10.1149/2.075203jes] All rights reserved.
Transient Effect Assisted NBTI Degradation in p-Channel LTPS TFTs under Dynamic Stress
(2011)
Lin, Chia-Sheng
;
Chen, Ying-Chung
;
Chang, Ting-Chang
;
Li, Hung-Wei
;
Chen, Shih-Ching
This work investigates dynamic negative bias temperature instability (NBTI) in p-channel low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs) with different rise and fall times. Experimental results reveal identical increases in the interface state density (N(it)) induced by different dynamic NBTI stress conditions. Nevertheless, the degradation of the grain boundary trap (N(trap)) becomes more significant as rise time decreases to 1 mu s. Because the surface inversion layer cannot form during the short rise time, transient bulk voltage will cause excess holes to diffuse into the poly-Si bulk. Therefore, the significant N(trap) increase is assisted by this transient effect. (c) 2010 The Electrochemical Society. [DOI: 10.1149/1.3507253] All rights reserved.
Unusual Threshold Voltage Shift Caused by Self-Heating-Induced Charge Trapping Effect
(2010)
Jian, Fu-Yen
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Chang, Ting-Chang
;
Chu, An-Kuo
;
Chen, Te-Chih
;
Chen, Shih-Ching
This article investigates the threshold voltage (V(t)) shift induced by a self-heating effect for n-channel low temperature poly-Si thin film transistors (TFTs) and finds that there is a shift of more than 3 V in the negative direction after a self-heating operation of 100 ms. The negative V(t) shift can be attributed to the charge-trapping effect caused by the holes generated by trap-assisted band-to-band thermionic field emission and trapped in the grain boundary of the poly-Si film substrate. We used lateral body contact structure to verify that this unusual V(t) shift is related to the holes trapped in the substrate. (C) 2010 The Electrochemical Society. [DOI: 10.1149/1.3290686] All rights reserved.