Browsing by Author "Lin, Chia-Yi"

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A CMOS-Compatible Poly-Si Nanowire Device with Hybrid Sensor/Memory Characteristics for System-on-Chip Applications
(2012-04-01)
Chen, Min-Cheng
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Chen, Hao-Yu
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Lin, Chia-Yi
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Chien, Chao-Hsin
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Hsieh, Tsung-Fan
This paper reports a versatile nano-sensor technology using "top-down" poly-silicon nanowire field-effect transistors (FETs) in the conventional Complementary Metal-Oxide Semiconductor (CMOS)-compatible semiconductor process. The nanowire manufacturing technique reduced nanowire width scaling to 50 nm without use of extra lithography equipment, and exhibited superior device uniformity. These n type polysilicon nanowire FETs have positive pH sensitivity (100 mV/pH) and sensitive deoxyribonucleic acid (DNA) detection ability (100 pM) at normal system operation voltages. Specially designed oxide-nitride-oxide buried oxide nanowire realizes an electrically Vth-adjustable sensor to compensate device variation. These nanowire FETs also enable non-volatile memory application for a large and steady Vth adjustment window (>2 V Programming/Erasing window). The CMOS-compatible manufacturing technique of polysilicon nanowire FETs offers a possible solution for commercial System-on-Chip biosensor application, which enables portable physiology monitoring and in situ recording.
A Generic Multi-Dimensional Scan-Control Scheme for Test-Cost Reduction
(2011-11-01)
Lin, Chia-Yi
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Chen, Hung-Ming
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
This paper proposes a generic multi-dimensional scan shift control concept for multiple scan chain design. Multiple scan chain test scheme provides very low scan power by skipping (selectively load/unload) many long scan chain switching activities. Based on the two-dimensional scan shift control, we can achieve low test power with simple and small overhead structure. We can further extend the scheme to a generic N dimension test scheme. The proposed scheme skips many unnecessary don't care (X) patterns to reduce the test data volume and test time. The experimental results of the proposed 2-D scheme achieve significant improvement in shift power reduction, test volume and test time reduction. Compared with traditional single scan chain design, the large benchmark b17 of ITC'99 has over 50% reduction in test data volume and over 40% reduction in test time with little area overhead, around 1% routing overhead, and the power reduction is over 97%.
A Novel Two-Dimensional Scan-Control Scheme for Test-Cost Reduction
(2010)
Lin, Chia-Yi
;
Chen, Hung-Ming
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper proposes a two-dimensional scan shift control concept for multiple scan chain design. Multiple scan chain test scheme provides very low scan power by skipping many long scan chain switching activities. Based on two-dimensional scan shift control, we can achieve low test power with simple and small overhead structure. The proposed scheme skips many unnecessary don\'t care (X) patterns to reduce the test data volume and test time. The experimental results of the proposed scheme illustrate the significant improvement in shift power reduction, test volume and test time reduction. Compared with traditional single scan chain design, the large benchmark b17 of ITC\'99 has over 50% reduction in test data volume and over 40% reduction in test time with little area overhead and very few extra pins, and the power reduction is over 97%.
A selective pattern-compression scheme for power and test-data reduction
(2007)
Lin, Chia-Yi
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Chen, Hung-Ming
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
This paper proposes a selective pattern-compression scheme to minimize both test power and test data volume during scan-based testing. The proposed scheme will selectively supply the test patterns either through the compressed scan chain whose scanned values will be decoded to the original scan cells, or directly through the original scan chain using minimum transition filling method. Due to shorter length of a compressed scan chain, the potential switching activities and the required storage bits can be both reduced. Furthermore, the proposed scheme also supports multiple scan chains. The experimental results demonstrate that, with few hardware overhead, the proposed scheme can achieve significant improvement in shift-in power reduction and large amount of test data volume reduction.
A Simple Method to Measure Pretilt Angles of Inverse Twisted Nematic Liquid Crystal Cells
(2014-12-01)
Wang, Sheng-Ya
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Lin, Chia-Yi
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Yang, Kei-Hsiung
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交大名義發表
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National Chiao Tung University
We have developed a simple optical method based on measurements of phase retardation[1] versus out-of-plane cell rotation angle and data analyzed by extended Jones matrix method to obtain pretilt angles of inverse twisted nematic (ITN) and tilted homeotropic liquid crystal (LC) cells. In our Jones-matrix calculations, we have assumed a constant pretilt angle as the LC-director tilt angles throughout the ITN cell as well as the tilted homeotropic cell. We have compared the measured pretilt angles of the ITN cell with those of an accompanying tilted homeotropic (ATH) cell. The results showed increasing discrepancies between them with increasing rubbing depth for LC alignments. However, these discrepancies could be explained by assuming that the surface-LC tilt angle of the ITN cell was equal to the measured pretilt angle of the ATH cell to generate a convex-type LC-director-deformation profile within the ITN cell based on Oseen-Frank elastic continuum theory with infinite anchoring energies. The average of the LC-director tilt angles over this profile was equivalent to the measured pretilt angle of the ITN cell.
A simulation analysis for the re-solving issue of the network revenue management problem
(2014-06-01)
Huang, Kuancheng
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Lin, Chia-Yi
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運輸與物流管理系註：原交通所+運管所
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Department of Transportation and Logistics Management
The classic dynamic programming approach is not applicable to the airline network revenue management (RM) problem of a practical size due to the curse of dimensionality. Many heuristic methods, including the most popular bid-price control approach, generate the approximate control decisions based on various static formulations, which need to be re-solved to take into account the dynamic features of the problem. By a simulation experiment, this study examines the re-solving issue of the bid-price method and tests a new method, the parameterized function approach, in which no problem-resolving is required. Based on the results, the parameterized function approach is found to be a promising alternative. As for the bid-price control approach, a high re-solving frequency is needed for a good result. (C) 2014 Elsevier Ltd. All rights reserved.
Estimating the Detection Stability of a Si Nanowire Sensor Using an Additional Charging Electrode
(2013)
Chen, Min-Cheng
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Chen, Hsiao-Chien
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Lee, Ta-Hsien
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Lin, Yu-Hsien
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Shih, Jyun-Hung
This paper proposes a sensing stability estimation method that involves using an additional forcing electrode to simulate the surface charge coupling effect for bottom gate nanowire sensors. The alteration of the Si nanowire can be observed by using the charging electrode without any complex surface treatment and micro-channel setup. The nanowire sensor has a distinct charge-sensitive slope (V-th shift > 60 mV/10(-16)C) with a wire-width scaling of 35 nm. The proposed estimation technique simplifies the charge sensing operation.
Fabrication of High-Sensitivity Polycrystalline Silicon Nanowire Field-Effect Transistor pH Sensor Using Conventional Complementary Metal-Oxide-Semiconductor Technology
(2011-04-01)
Chen, Hou-Yu
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Lin, Chia-Yi
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Chen, Min-Cheng
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Huang, Chien-Chao
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Chien, Chao-Hsin
High-sensitivity polycrystalline silicon (poly-Si) nanowire field-effect transistor (NW FET) pH sensors using top-down and self-aligned fabrication approaches involving the conventional complementary metal-oxide-semiconductor (CMOS) process are reported. For the top-down NW FET, the shrinkage due to reoxidation enables the nanowire width to be scaled to 40 nm without requiring the use of extra lithography equipment, and this improves the electrical uniformity and the performance of the sensors. The surface-ionic coupling operation of this buried-channel field-effect sensor exhibits superior pH sensitivity (threshold voltage shift > 100 mV/pH) as compared to the surface-channel ion-sensitive FET (ISFET). In addition, we report a novel method for fabricating self-aligned, vertical-channel, poly-Si nanowire sensors. The resulting 65-nm self-aligned vertical-channel poly-Si device was found to be feasible for independent-gate bias control, thus enabling its possible integration in very-large-scale integration (VLSI) circuits. Both the abovementioned approaches enable the manufacture of nanowire devices on a large-scale integrated (LSI) circuit using only CMOS manufacturing processes; this provides a high sensitivity, compact and cost-efficient biosensor systems-on-a-chip application. (C) 2011 The Japan Society of Applied Physics
Fabrication of High-Sensitivity Polycrystalline Silicon Nanowire Field-Effect Transistor pH Sensor Using Conventional Complementary Metal-Oxide-Semiconductor Technology (vol 50, 04DL05, 2011)
(2018-05-01)
Chen, Hou-Yu
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Lin, Chia-Yi
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Chen, Min-Cheng
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Huang, Chien-Chao
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Chien, Chao-Hsin
Femtosecond Transient Absorption Spectra and Dynamics of Carrier Relaxation of Tin Perovskites in the Absence and Presence of Additives
(2020-07-16)
Narra, Sudhakar
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Jokar, Efat
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Pearce, Orion
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Lin, Chia-Yi
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Fathi, Amir
The effects of additives SnF2 (10%) and EDAI(2) (1%) on the dynamics of carrier relaxation of formamidinium tin triiodide (FASnI(3)) perovskite were studied using femtosecond transient absorption spectra (TAS) with excitation at 600 and 870 nm. The TAS were analyzed according to a parallel sequential kinetic model with a global fit through singular-value decomposition. For excitation at 600 nm, two relaxation paths were found: one involved hot and cold carriers in the bulk state undergoing shallow bulk-defect-mediated charge recombination; the other involved trap carriers in the surface state undergoing deep surface-defect-mediated charge recombination. For excitation at 870 nm, only cold carriers were subjected to the bulk-state relaxation channel. Our spectral results indicate significant effects of the additives on retarding charge recombination in both bulk and surface states as well as decreasing the bandgap renormalization energy, the bandwidth of the photobleaching (PB) band, and the Stokes shift between the PB and photoluminescence bands, explaining how the device performance of FASnI(3) solar cells became enhanced in the presence of SnF2 and EDAI(2).
Higher NAFLD fibrosis score is associated with impaired eGFR
(2020-01-01)
Hsieh, Meng-Hsuan
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Wu, Kuan-Ta
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Chen, Yi-Yu
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Yang, Jeng-Fu
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Lin, Wen-Yi
Background/Purpose: Chronic kidney disease (CKD) has become a worldwide health problem, leading to high morbidity and mortality, and non-alcoholic fatty liver disease (NAFLD) is considered a risk factor for CKD. The aim of this study was to explore the relationship between NAFLD fibrosis score (NFS) and the estimated glomerular filtration rate (eGFR), and identify possible risk factors related to the NFS among Taiwanese subjects. Methods: Subjects were enrolled from the database of the Department of Preventive Medicine of Kaohsiung Municipal Hsiao-Kang Hospital. The eGFR was calculated according to the Taiwanese Modification of Diet in Renal Disease (TMDRD) equation, and the NFS was employed to evaluate the fibrotic level. Results: In total, 11,376 subjects were enrolled in this study, with a mean age of 52.0 +/- 6.81 years, including 4529 (39.8%) males. A fasting sugar level >= 100 mg/dL (OR = 1.70, 95% CI = 1.52-1.87) and an abnormal waist circumference (OR = 1.81, 95% CI = 1.65-1.99) were significant factors associated with NFS (p < 0.05). Trends of a decreasing TMDRD score and an increasing NFS with increasing age were noted (p < 0.05). The NFS was significantly negatively correlated with the TMDRD score (standard coefficients: -0.067, p < 0.001). Conclusion: A higher NFS is associated with an impaired eGFR in Taiwanese subjects. Controlling risk factors, especially fasting sugar level and waist circumference, may be useful in preventing NFS deterioration, which is negatively correlated with the eGFR. Copyright (C) 2019, Formosan Medical Association. Published by Elsevier Taiwan LLC.
Hybrid Si/TMD 2D Electronic Double Channels Fabricated Using Solid CVD Few-Layer-MoS2 Stacking for V-th Matching and CMOS-Compatible 3DFETs
(2014)
Chen, Min-Cheng
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Lin, Chia-Yi
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Li, Kai-Hsin
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Li, Lain-Jong
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Chen, Chang-Hsiao
Stackable 3DFETs such as FinFET using hybrid Si/MoS 2 channels were developed using a fully CMOS-compatible process. Adding several molecular layers (3-16 layers) of the transition-metal dichalcogenide (TMD), MoS2 to Si fin and nanowire resulted in improved (+25%) I-on,I-n of the FinFET and nanowire FET (NWFET). The PFETs also operated effectively and the N/P device V-th are low and matched perfectly. The proposed heterogeneous Si/TMD 3DFETs can be useful in future electronics.
Nickel Silicide Formation using Pulsed Laser Annealing for nMOSFET Performance Improvement
(2011)
Chen, Hou-Yu
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Lin, Chia-Yi
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Chen, Min-Cheng
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Huang, Chien-Chao
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Chien, Chao-Hsin
The formation of a uniform, high tensile stress and low silicide/Si interfacial resistance nickel silicide in nMOSFET by introducing pulsed laser annealing (PLA) is reported. This annealing approach facilitated the phase transformation of nickel silicide to Si-rich NiSi(x) compounds using a low-thermal-budget process, improves the silicide/Si interface regularity and avoids familiar (111) NiSi(2) facet formation at a laser energy of 1.5 J cm(-2). By increasing laser energy density up to 2.3 J cm(-2), the device performance and statistics junction leakage distribution were degraded due to the increased sheet resistance of silicide layer and the destroyed silicide/Si interface morphology. When the PLA with a laser energy density of 1.5 J cm(-2) was employed for nickel silicidation on the p-type Schottky diodes, a 0.16 eV hole Schottky barrier height (SBH) increase from 0.52 to 0.68 eV was observed. In addition, the application of PLA for source/drain silicidation of nMOSFETs demonstrated an 8% enhancement in I(on) I(off) characteristic relative to that obtained through the conventional two-step rapid thermal annealing (RTA). This PLA method holds promise as a potential replacement for current nickel silicide annealing approaches toward extremely scaled-down transistors. (C) 2011 The Electrochemical Society. [DOI: 10.1149/1.3601849] All rights reserved.
On Reducing Test Power and Test Volume by Selective Pattern Compression Schemes
(2010-08-01)
Lin, Chia-Yi
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Lin, Hsiu-Chuan
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Chen, Hung-Ming
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
In modern chip designs, test strategies are becoming one of the most important issues due to the increase of the test cost, among them we focus on the large test power dissipation and large test data volume. In this paper, we develop a methodology to suppress the test power to avoid chip failures caused by large test power, and our methodology is also effective in reducing the test data volume and shift-in power. The proposed schemes and techniques are based on the selective test pattern compression, they can reduce considerable shift-in power by skipping the switching signal passing through long scan chains. The experimental results with ISCAS89 circuits demonstrate that our methodology can achieve significant improvement in the reduction of shift-in power and test data volume. Our approach also supports multiple scan chains.
On Reducing Test Power, Volume and Routing Cost by Chain Reordering and Test Compression Techniques
(2010-03-01)
Lin, Chia-Yi
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Hsu, Li-Chung
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Chen, Hung-Ming
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
With the advancement of VLSI manufacturing technology entire electronic systems can be Implemented in a single intergrated circuit Due to the complexity in SoC design. circuit testability becomes one of the most challenging works Without careful planning it Design For Testability (DFT) design, circuits consume mote power in test mode operation than that in normal functional mode This elevated testing power may cause problems including overall yield lost and instant circuit damage In this paper, we present two approaches to minimize scan based DFT power dissipation First methodology Includes routine cost consideration in scan chain reordering after cell placement. while second methodology provides test pattern compression for lower power We formulate the first problem as a Traveling Salesman Problem (TSP). with different cost evaluation from [18],[19] and apply an efficient heuristic to solve it lit the second problem we provide a selective scan chain architecture and perform a simple yet effective encoding scheme for lower scan testing power dissipation The experimental results of ISCAS'89 benchmarks show that the first methodology obtains up to 10% average power saving under the same low routing cost compared with a recent result in [19] The second methodology reduces over 17% of test power compared with filling all don't care (X) bit with 0 in one of ISCAS'89 benchmarks We also provide the integration flow of these two approaches in this paper
Random Telegraph Noise in 1X-nm CMOS Silicide Contacts and a Method to Extract Trap Density
(2012-04-01)
Chen, Min-Cheng
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Lin, Chia-Yi
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Chen, Bo-Yuan
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Lin, Chang-Hsien
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Huang, Guo-Wei
The behavior of random telegraph noise was affected by nickel silicide barrier height engineering in advanced nano-CMOS technologies. Contact resistance fluctuations with magnitude of up to 40% were observed when a Schottky barrier was reduced to 0.2 eV. The large contact resistance instability is attributed to the barrier modification by positive charge trapping and detrapping in a Schottky contact. The prevalence and magnitude of the noise are dependent on the contact area, trap density, trap energy, and the silicide Schottky barrier height. In this letter, we propose a fast method to extract the density of responsible contact traps.
Separating spectral mixtures in hyperspectral image data using independent component analysis: validation with oral cancer tissue sections
(2013-12-01)
Duann, Jeng-Ren
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Jan, Chia-Ing
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Ou-Yang, Mang
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Lin, Chia-Yi
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Mo, Jen-Feng
Recently, hyperspectral imaging (HSI) systems, which can provide 100 or more wavelengths of emission autofluorescence measures, have been used to delineate more complete spectral patterns associated with certain molecules relevant to cancerization. Such a spectral fingerprint may reliably correspond to a certain type of molecule and thus can be treated as a biomarker for the presence of that molecule. However, the outcomes of HSI systems can be a complex mixture of characteristic spectra of a variety of molecules as well as optical interferences due to reflection, scattering, and refraction. As a result, the mixed nature of raw HSI data might obscure the extraction of consistent spectral fingerprints. Here we present the extraction of the characteristic spectra associated with keratinized tissues from the HSI data of tissue sections from 30 oral cancer patients (31 tissue samples in total), excited at two different wavelength ranges (330 to 385 and 470 to 490 nm), using independent and principal component analysis (ICA and PCA) methods. The results showed that for both excitation wavelength ranges, ICA was able to resolve much more reliable spectral fingerprints associated with the keratinized tissues for all the oral cancer tissue sections with significantly higher mean correlation coefficients as compared to PCA (p < 0.001). (C) The Authors.
Silicide Barrier Engineering Induced Random Telegraph Noise in 1Xnm CMOS Contacts
(2011)
Chen, Min-Cheng
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Lin, Chia-Yi
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Chen, Bo-Yuan
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Lin, Chang-Hsien
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Huang, Guo-Wei
For the first time, new random telegraph noise behaviors are reported for silicide band gap engineering in advanced nano CMOS technology. Noise current pulses of up to 40% magnitude are observed when Schottky barrier is reduced to 0.2eV. The large contact resistance instability is attributed to barrier modification at Schottky contact interface by positive charge trapping. The prevalence and magnitude of the noise are dependent on the contact size, trap density, trap energy and the silicide Schottky barrier height. In this work, we report a fast monitor methodology to identify the silicide process induced traps in small silicide contacts for 1Xnm CMOS technology.
The effect of pulsed laser annealing on the nickel silicide formation
(2010-12-01)
Chen, Hou-Yu
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Lin, Chia-Yi
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Huang, Chien-Chao
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Chien, Chao-Hsin
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電子工程學系及電子研究所
The pulsed laser annealing (PLA) is used to assist nickel silicide transformation for Schottky barrier height reduction and tensile strain enhancement and the effect of different laser power are investigated. In this report, a two-step annealing process which combine the conventional rapid thermal annealing with pulsed laser annealing is proposed to achieve a smooth silicon-rich NiSi(x) interfacial layer on (1 0 0) silicon. With optimized laser energy, a 0.2 eV Schottky barrier height (SBH) modulation is observed from Schottky diode electrical characterization. Furthermore. PLA provides sufficient effective temperature during silicidation which also lead to increased tensile stress of silicide film than the two-step RTA silicide is also investigated. The SBH modulation and tensile stress enhancement benefits of PLA silicidation are considered as an alternative to the conventional rapid thermal annealing for ultra-scaled devices performance enhancement. (C) 2010 Elsevier B.V. All rights reserved.