Browsing by Author "Lin, Chien-Ching"

Now showing 1 - 18 of 18

A 0.22nJ/b/iter 0.13 mu m turbo decoder chip using inter-block permutation interleaver
(2007)
Wong, Cheng-Chi
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Tang, Cheng-Hao
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Lai, Ming-Wei
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Zheng, Yan-Xiu
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Lin, Chien-Ching
This paper presents a high speed turbo decoder containing 32 MAP decoders with a inter-block permutation interleaver. The proposed butterfly network guarantees contention-free property and promises parallel processing of turbo decoder without performance degradation. In addition, our approach also features a relocated radix-2 x 2 ACS structure to reduce the critical path delay. After manufacturing by 0.13 mu m CMOS process, the test results show the energy efficiency is 0.22nJ/b/iter in the 160Mb/s data rate.
A Long Block Length BCH Decoder for DVB-S2 Application
(2009)
Lin, Yi-Min
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Wu, Jau-Yet
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Lin, Chien-Ching
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Chang, Hsie-Chia
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電子工程學系及電子研究所
In this paper, a low-complexity and full-mode BCH decoder with long block length for DVB-S2 application is presented. With the reversed error locator polynomial, our proposed reversed Berlekamp-Massey algorithm features a sharing architecture to perform parallel-4 syndrome and Chien search calculations. Concatenated with the LDPC decoder, which has a long decoding latency and a short period of data output time, the proposed parallel-4 BCH decoder ensures the sufficient throughput with only one bank memory. Moreover, a composite field divider instead of a large Galois field inversion table is also presented to reduce complexity. After implemented in 0.13 mu m CMOS technology, our parallel-4 BCH decoder occupied 44K gate count can reach 380Mb/s according to the post-layout simulations.
A low-power Viterbi decoder based on scarce state transition and variable truncation length
(2007)
Lin, Dah-Jia
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Lin, Chien-Ching
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Chen, Chih-Lung
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Chang, Hsie-Chia
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Lee, Chen-Yi
The ACS computation and the survivor memory are most power critical, consuming about 90% power in the Viterbi decoder. Based on the low power mechanisms, the scarce state transition (SST) technique and the variable truncation length, we present a Viterbi decoder for the MB-OFDM UWB applications. The SST scheme lowers state transition as well as signal switches in the ACS units. Moreover, the decoding with variable truncation length leads to the access reduction in the survivor memory. The experimental results show more than 30% power reduction under high SNRs as compared to those without SST and variable truncation length.
A Universal VLSI Architecture for ReedSolomon Error-and-Erasure Decoders
(2009-09-01)
Chang, Hsie-Chia
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Lin, Chien-Ching
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Chang, Fu-Ke
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Lee, Chen-Yi
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電子工程學系及電子研究所
This paper presents a universal architecture for Reed-Solomon (RS) error-and-erasure decoder. In comparison with other reconfigurable RS decoders, our universal approach based on Montgomery multiplication algorithm can support not only arbitrary block length but various finite-field degree within different irreducible polynomials. Moreover, the decoder design also features the constant multipliers in the universal syndrome calculator and Chien search block, as well as an on-the-fly inversion table for calculating error or errata values. After implemented with 0.18-mu m 1P6M technology, the proposed universal RS decoder correcting up to 16 errors can be measured to reach a maximum 1.28 Gb/s data rate at 160 MHz. The total gates count is around 46.4 K with 1.21 mm silicon area, and the average core power consumption is 68.1 mW.
Design of a Multimode QC-LDPC Decoder Based on Shift-Routing Network
(2009-09-01)
Liu, Chih-Hao
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Lin, Chien-Ching
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Yen, Shau-Wei
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Chen, Chih-Lung
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Chang, Hsie-Chia
A reconfigurable message-passing network is proposed to facilitate message transportation in decoding multimode quasi-cyclic low-density parity-check (QC-LDPC) codes. By exploiting the shift-routing network (SRN) features, the decoding messages are routed in parallel to fully support those specific 19 and 3 submatrix sizes defined in IEEE 802.16e and IEEE 802.11n applications with less hardware complexity. A 6.22-mm(2) QC-LDPC decoder with SRN is implemented in a 90-nm 1-Poly 9-Metal (1P9M) CMOS process. Postlayout simulation results show that the operation frequency can achieve 300 MHz, which is sufficient to process the 212-Mb/s 2304-bit and 178-Mb/s 1944-bit codeword streams for IEEE 802.16e and IEEE 802.11n systems, respectively.
Method and apparatus for self-compensation on belief-propagation algorithm
(2007-12-06)
Liao, Yen-Chin
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Lin, Chien-Ching
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Chang, Hsie-Chia
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Liu, Chih-Wei
A self-compensation method includes: firstly using a min-sum algorithm to derive multiple output values in order to approach a operational result of the checking side of a belief-propagation; and then checking the present iteration number of decoding based on a checking rule; and finally, if in the previous step the present iteration number is identified with a to-be-corrected state, then performing a compensation procedure on the multiple output values, wherein the compensation term is dynamically selected in accordance with an input value of the checking nodes of the belief-propagation. The invention also provides an automatic compensation apparatus, which consists of devices such as a min-sum operating unit, and a dynamic quantization control unit, etc., which can be used, while executing the invented method described above, to decode the belief-propagation algorithm.
Method and apparatus for switching data in communication system
(2008-08-21)
Lee, Chen-Yi
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Lu, Jr-Hau
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Lin, Chien-Ching
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Chang, Hsie-Chia
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Hsu, Yar-Sun
A method and apparatus for switching data in communication system which comprises of mainly a conversion circuit to receive the source data possessing in a real coding dimension and covert it to converted the data possessing in a tolerable coding dimension; the judgment bits are set in the converted data to designate the data as source data or not. Later on, shifter circuit is used to shift the converted data in certain amount and generates a shifted data; meanwhile, the right side and left side of shifted data are used to start acquiring the real coding dimension to be used respectively as a first data and a second data. Finally, a comparison and selection circuit is used to compare the corresponding judgment bits in the first and the second data and to output an output data, wherein output data is source data with the above-mentioned amount of shift.
Method and apparatus for switching data in communication system
(2008-08-21)
Lee, Chen-Yi
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Liu, Chih-Hao
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Lin, Chien-Ching
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Chang, Hsie-Chia
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Hsu, Yar-Sun
A method and apparatus for switching data in communication system which comprises of mainly a conversion circuit to receive source data possessing real coding dimension and covert it to converted data possessing tolerable coding dimension; judgment bit is set in the converted data to designate the data as source data or not. Later on, shift circuit is used to shift the converted data in certain amount so as to generate a shifted data; meanwhile, the lowest bit and highest bit of shifted data are used to start acquiring real coding dimension to be used respectively as a first data and a second data, or by changing the pattern of acquiring the first data, then the highest bit minus the real coding dimension bit as the starting bit of the first data, and acquiring the real coding dimension from the side of the lowest bit. Finally, a comparison and selection circuit is used to compare the corresponding judgment bit in the first and the second data and to output an output data, wherein output data is source data with the above-mentioned amount of shift.
Method for calculating syndrome polynomial in decoding error correction codes
(2003-12-11)
Chang, Hsie-Chia
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Lee, Chen-Yi
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Lin, Chien-Ching
The present invention provides a method of calculating the syndrome polynomial in decoding error correction codes. From the relation between the syndromes and the coefficients of the error locator polynomial, the inference that the first t syndromes are zeros, then the next t syndromes are also zeros can be deduced, wherein t is the largest number of correctable errors. For all received codewords, the first t syndromes are calculated. Next, whether the first t syndromes are zeros is judged. If the first t syndromes are zeros, the computation is stopped; otherwise, the next t syndromes are calculated. Therefore, the present invention can judge whether the received codeword is erroneous with only a half of computation, hence effectively reducing the computation in practical operation and achieving the object of low power consumption.
Method for updating check-node of low-density parity-check (LDPC) codes decoder and device using the same
(2006-10-26)
Lee, Chen-Yi
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Lin, Chien-Ching
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Lin, Kai-Li
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Chang, Hsie-Chia
The invention provides a method for updating check-node of low-density parity-check (LDPC) codes decoder. The method comprises the following steps: First of all, sort all data that are input into the check-node of LDPC codes decoder to find a minimum absolute value and a second minimum absolute value. Secondly, compare each of all the data to both of the minimum absolute value. If the compared data is equivalent to the current minimum absolute value, the compared data is updated by the secondary minimum absolute value. Otherwise, the compared data is updated by the minimum absolute value.
MLP/BP-based soft decision feedback equalization with bit-interleaved TCM for wireless applications
(2007-04-01)
Hsu, Terng-Ren
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Lin, Chien-Ching
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Hsu, Terng-Yin
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Lee, Chen-Yi
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資訊工程學系
For more efficient data transmissions, a new MLP/BP-based channel equalizer is proposed to compensate for multi-path fading in wireless applications. In this work, for better system performance, we apply the soft output and the soft feedback structure as well as the soft decision channel decoding. Moreover, to improve packet error rate (PER) and bit error rate (BER), we search for the optimal scaling factor of the transfer function in the output layer of the MLP/BP neural networks and add small random disturbances to the training data. As compared with the conventional MLP/BP-based DFEs and the soft output MLP/BP-based DFEs, the proposed MLP/BP-based soft DFEs under multi-path fading channels can improve over 3-0.6 dB at PER=10(-1) and over 3.3-0.8 dB at BER=10(-3).
Multi-mode message passing switch networks applied for QC-LDPC decoder
(2008)
Liu, Chih-Hao
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Lin, Chien-Ching
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Chang, Hsie-Chia
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Lee, Chen-Yi
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Hsu, Yarsun
The multi-mode message passing switch networks for multi-standard QC-LDPC decoder are presented. An enhanced self-routing switch network with only one barrel shifter permutation structure and a shifter-based two-way duplicated switch network are proposed to support 19 and 3 different submatrices defined in IEEE 802.16e and IEEE 802.11n. These proposed switch networks can route the decoding message in parallel by different sizes without signal congestion. The enhanced self-routing switch network can switch the messages at different expansion factors with the lowest hardware complexity. Under the condition of a smaller expansion factor, the decoder throughput can be enhanced from the two-way duplicated switch network by increasing the parallelism. In the 130nm CMOS synthesis result, the proposed enhanced self-routing and the two-way duplicated switch network gate counts are 21.9k and 37.4k at 384MHz operation frequency.
MULTI-MODE MULTI-PARALLELISM DATA EXCHANGE METHOD AND DEVICE THEREOF
(2009-06-11)
LIU, Chih-Hao
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Lin, Chien-Ching
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Lee, Chen-Yi
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Chang, Hsie-Chia
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Hsu, Yarsun
A multi-mode multi-parallelism data exchange method and the device thereof are proposed to apply to a check node operator or a bit node operator. The proposed method comprises the steps of: duplicating part or all of an original shift data as a duplicated shift data; combining the original shift data and the duplicated shift data to form a data block; and using a data block as the unit to shift this data block so as to conveniently retrieve shift data from the shifted data block. With a maximum z factor circuit and duplication of part of data, specifications of different shift sizes can be supported. The functions of shifters of several sizes can therefore be accomplished with the minimum complexity.
Self-compensation technique for simplified belief-propagation algorithm
(2007-06-01)
Liao, Yen-Chin
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Lin, Chien-Ching
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Chang, Hsie-Chia
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Liu, Chih-Wei
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電子工程學系及電子研究所
The min-sum algorithm is the most common method to simplify the belief-propagation algorithm for decoding low-density parity-check (LDPC) codes. However, there exists a performance gap between the min-sum and belief-propagation algorithms due to nonlinear approximation. In this paper, a self-compensation technique using dynamic normalization is thus proposed to improve the approximation accuracy. The proposed scheme scales the min-sum algorithm by a dynamic factor that can be derived theoretically from order statistics. Moreover, applying the proposed technique to several LDPC codes for DVB-S2 system, the average signal-to-noise ratio degradation, which results from approximation inaccuracy and quantization error, is reduced to 0.2 dB. Not only does it enhance the error-correcting capability of the min-sum algorithm, but the proposed self-compensation technique also preserves a modest hardware cost. After realized with 0.13-mu m standard cell library, the dynamic normalization requires about 100 additional gates for each check,node unit in the min-sum algorithm.
SoC for COFDM wireless communications: Challenges and opportunities
(2006)
Lee, Chen-Yi
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Liu, Hsuan-Yu
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Lin, Chien-Ching
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
Coded Orthogonal Frequency Division Multiplexing (COFDM) technology has been widely accepted in many communication systems due to both bandwidth efficiency and robustness to channel distortion. This opens a great of opportunities for SoC society to deal with design complexity by exploiting benefits of giga-scale integration. In this paper, we'll first review the general design concept of COFDM systems and then highlight several key issues in SoC realization. Then a system-level design flow by taking into account both performance indices and hardware complexity will be introduced. Several core modules related to COFDM system will also be addressed to see how better solutions can be achieved, especially for wireless applications. Finally two case studies on WLAN and OFDM-UWB will be discussed to demonstrate our proposals as well as to provide some directions for further research.
Transmission method combining trellis coded modulation and low-density parity check code and architecture thereof
(2006-10-19)
Lin, Chien-Ching
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Chang, Hsie-Chia `
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Lee, Chen-Yi
The present invention discloses a method combining Trellis Coded Modulation (TCM) and Low-Density Parity Check (LDPC) code and the architecture thereof, which incorporates TCM with LDPC code having better error-correction capability to promote transmission quality and to define TCM of different transmission rates. Further, TCM can utilize less number of states to outperform the conventional spreading so that the hardware complexity in high-speed transmission can be reduced.
Turbo Decoder Using Contention-Free Interleaver and Parallel Architecture
(2010-02-01)
Wong, Cheng-Chi
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Lai, Ming-Wei
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Lin, Chien-Ching
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Chang, Hsie-Chia
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Lee, Chen-Yi
This paper introduces a turbo decoder that utilizes multiple soft-in/soft-out (SISO) decoders to decode one codeword. In addition, each SISO decoder is modified to allow simultaneous execution over multiple successive trellis stages. The design issues related to the architecture with parallel high-radix SISO decoders are discussed. First, a contention-free interleaver for the hybrid parallelism is presented to overcome the complicated collision problem as well as reduce interconnection network complexity. Second, two techniques for the high-speed add-compare-select (ACS) circuits are given to lessen area overhead of the SISO decoder. Third, a modification of the processing schedule is made for higher operating efficiency. Two designs with parallel architecture have been implemented. The first design with 32 SISO decoders, each of which processes 2 symbols per cycle, has 160 Mb/s and 0.22 nJ/b/iter after measurement. The second design uses 16 SISO decoders to deal with 4 symbols per cycle and achieves 100% efficiency, leading to 1000 Mb/s and 0.15 nJ/b/iter in post-layout simulation.
Universal architectures for Reed-Solomon error-and-erasure decoder
(2005)
Chang, Fu-Ke
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Lin, Chien-Ching
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Chang, Hsie-Chia
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Lee, Chen-Yi
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電子工程學系及電子研究所
This paper presents the universal architecture for Reed Solomon (RS) error-and-erasure decoder that can accommodate any codeword with different code parameters and finite field definitions. In comparison with other reconfigurable RS decoders, the proposed design, based on the Montgomery multiplication algorithm, can support various finite field degrees, different primitive polynomials, and erasure decoding functions. In addition, the decoder features an on-the-fly finite field inversion table for high speed error evaluation. The area efficient design approach is also presented Implemented with 1.2V 0.13 mu m 1P8M technology, this decoder, correcting up to 16 errors, can operate at 300MHz and reach a 2.4Gb/s data rate. The total gate count is about 54K and the core size is 0.36mm(2). The average power consumption is 20.2m W.