Browsing by Author "Lin, Chih-Chih"

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A Novel Structure to Reduce Degradation Under Mechanical Bending in Foldable Low Temperature Polysilicon TFTs Fabricated on Polyimide
(2020-05-01)
Wang, Yu-Xuan
;
Chang, Ting-Chang
;
Huang, Shin-Ping
;
Tai, Mao-Chou
;
Zheng, Yu-Zhe
In this study, a novel structural device, named as a wing-shaped TFT, is proposed and is demonstrated to prevent fast deterioration under mechanical bending in foldable devices. After long-term mechanical bending, standard low-temperature polysilicon TFTs exhibit instability behaviors such as sub-channel formation, serious threshold voltage shifts, an on-current (I-ON) increase, and an off-current (I-OFF) decrease. These phenomena are believed to be due to additional oxide traps along the channel-width edges of the gate insulator after bending. In order to suppress this degradation, a wing-shaped structure is proposed. By extending the active layer, degradation regions are shifted away from the main channel. Therefore, the reliability of the devices is enhanced. The transfer characteristics show enhanced electrical behavior after being held for 48 hours in a static bent condition, with an 88% drop in threshold voltage shift as well as a 55% decrease in subthreshold swing degradation, proving better durability of the foldable TFT to bending stress for devices with these wings. Time-dependent transfer characteristics, a COMSOL simulation, and device geometry are discussed to support our findings.
Abnormal hysteresis formation in hump region after positive gate bias stress in low-temperature poly-silicon thin film transistors
(2020-09-30)
Tu, Hong-Yi
;
Chang, Ting-Chang
;
Tsao, Yu-Ching
;
Tai, Mao-Chou
;
Tsai, Yu-Lin
Degradation in low-temperature polycrystalline-silicon thin-film transistors after electrical stress was thoroughly investigated in this work. Main channel degradation, abnormal hump generation and hysteresis appearing in the hump region can be observed after positive bias stress. Furthermore, the difference in subthreshold swing (SS) values between forward/reverse sweep is observed. The electron trapping into the gate insulator (GI) dominates the main degradation and the hump generation. Additionally, the difference in SS values which appears in the hump region is attributed to the interface traps and the hysteresis is caused by electron trapping/detrapping into GI.
Effect of a-InGaZnO TFT Channel Thickness under Self-Heating Stress
(2019-09-18)
Tai, Mao-Chou
;
Chang, Po-Wen
;
Chang, Ting-Chang
;
Tsao, Yu-Ching
;
Tsai, Yu-Lin
In this work, indium-gallium-zinc-oxide thin film transistors (IGZO-TFTs) with different channel thicknesses were compared after self-heating stress (SHS). Although TFTs with a thicker channel have higher current during stress conditions, less degradation is reported. This degradation, manifest as the threshold voltage shift in the transfer characteristics, is well described by the stretched-exponential equation. In addition, the average effective barrier height, Et, is extracted to compare the difference in degradation between both TFTs, and finds that the barrier height in the thick channel device is twice that of the thin channel device. Finally, a COMSOL simulation is performed to demonstrate the electrical difference at the gate insulator layer and confirm such phenomena. (C) 2019 The Electrochemical Society.
Interface Defect Shielding of Electron Trapping in a-InGaZnO Thin Film Transistors
(2020-09-01)
Lin, Chih-Chih
;
Tai, Mao-Chou
;
Chang, Ting-Chang
;
Tsao, Yu-Ching
;
Wang, Yu-Xuan
In this work, an abnormal lowering of subthreshold swing (SS) after self-heating stress in a device with thick channel is observed. A model of interface defect shielding is proposed, based on electron trapping at the channel/gate insulator interface. The phenomenon is discussed systematically through the band diagram and extractions of the field effective mobility. Results suggest that a depletion region appears after electron trapping at the front channel, which then prevents the carriers from reaching the interface defects. Therefore, an abnormal superior electrical performance after stress is observed. Finally, a dual gate amorphous InGaZnO (a-IGZO) thin film transistor (TFT) is used to clarify the phenomenon. Results from different top gate bias voltage confirms the bulk accumulation and better gate control.