Browsing by Author "Lin, Ching-Hao"

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10-ms 18-Band Quasi-ANSI S1.11 1/3-Octave Filter Bank for Digital Hearing Aids
(2013-03-01)
Liu, Chih-Wei
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Chang, Kuo-Chiang
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Chuang, Ming-Hsun
;
Lin, Ching-Hao
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電子工程學系及電子研究所
The ANSI S1.11 1/3-octave filter bank is suitable for digital hearing aids, but its large group delay and high computational complexity complicate matters considerably. This study presents a 10-ms 18-band quasi-ANSI S1.11 1/3-octave filter bank for processing 24 kHz audio signals. We first discuss a filter order optimization algorithm to define the quasi-ANSI filters. The group delay constraint of filters is limited to 10 ms. The proposed design adopts an efficient prescription-fitting algorithm to reduce inter-band interference, enabling the proposed quasi-ANSI filter bank to compensate any type of hearing loss (HL) using the NAL-NL1 or HSE prescription formulas. Simulation results reveal that the maximum matching error in the prescriptions of the mild HL, moderate HL, and severe-to-profound HL is less than 1.5 dB. This study also investigates the complexity-effective multirate IFIR quasi-ANSI filter bank. For an 18-band digital hearing aid with a 24 kHz sampling rate, the proposed architecture eliminates approximately 93% of the multiplications and up to 74% of the storage elements, compared with a parallel FIR filters architecture. The proposed analysis filter bank (AFB) was designed in UMC 90 nm CMOS high-VT technology, and on the basis of post-layout simulations, it consumes 73 mu W (@V-DD = 1 V). By voltage scaling (to 0.6 V), the simulation results show that the power consumption decreases to 27 mu W, which is approximately 30% of that consumed by the most energy-efficient AFB available in the literature for use in hearing aids.
Complexity-Effective Implementation of Programmable FIR Filters Using Simplified Canonic Signed Digit Multiplier
(2014-01-01)
Chang, Kuo-Chiang
;
Lin, Ching-Hao
;
Liu, Chih-Wei
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
This paper presents an energy-efficient FIR filter architecture which applies CSD multiplication to satisfy the design considerations of power consumption, flexibility and area cost. The proposed architecture reduces number of partial product rows and shift range of each coefficient multiplication to reduce energy consumption. However, the simplification restricts the use of filter coefficients. To mitigate this problem, this paper also presents a coefficient pre-processing flow to transform the original coefficients into applicable ones at design time to meet the restriction of the proposed multiplier. The simulation result reveals this technique can be applied for the computation of 97-tap filter. The design reduces up to 21.5% energy consumption per sample when compared with conventional Booth multiplier.