Browsing by Author "Lin, Geeng-Lih"

Now showing 1 - 7 of 7

ESD Protection Design with Latchup-Free Immunity in 120V SOI Process
(2015)
Huang, Yi-Jie
;
Ker, Ming-Dou
;
Huang, Yeh-Jen
;
Tsai, Chun-Chien
;
Jou, Yeh-Ning
Electrostatic discharge (ESD) protection with lowvoltage (LV) field-oxide devices in stacked configuration are proposed for high-voltage (HV) applications in a 0.5-mu m 120V SOI process. Stacked LV field-oxide devices with different stacking numbers have been verified in silicon chip to exhibit both of high ESD robustness and latchup-free immunity for HV applications.
Experimental evaluation and device simulation of device structure influences on latchup immunity in high-voltage 40-V CMOS process
(2006)
Hsu, Sheng-Fu
;
Ker, Ming-Dou
;
Lin, Geeng-Lih
;
Jou, Yeh-Ning
;
電機學院
The dependence of device structures and layout parameters on latchup immunity in high-voltage (HV) 40-V CMOS process have been verified with silicon test chips and investigated with device simulation. It was demonstrated that a specific test structure considering the parasitic silicon controlled rectifier (SCR) resulting from isolated asymmetric HV NMOS and HV PMOS has the best latchup immunity. The test structures and simulation methodology proposed in this work can be applied to extract safe and compact design rule for latchup prevention in HV CMOS process. All the test chips are fabricated in a 0.25-mu m 40-V CMOS technology.
Impact of Guard Ring Layout on the Stacked Low-Voltage PMOS for High-Voltage ESD Protection
(2015)
Liao, Seian-Feng
;
Tang, Kai-Neng
;
Ker, Ming-Dou
;
Yeh, Jia-Rong
;
Chiou, Hwa-Chyi
Electrostatic discharge (ESD) protection and latchup prevention are two important reliability issues to the CMOS integrated circuits, especially in high-voltage (HV) applications. In this work, the stacked low-voltage (LV) PMOS devices have been successfully verified in a 0.5-mu m HV process to provide high ESD level with high holding voltage for HV applications. In addition, the guard-ring layout on the stacked LV PMOS devices was further investigated in silicon chip to get high ESD robustness and latchup-free immunity for HV applications.
Improvement on ESD Robustness of Lateral DMOS in High-Voltage CMOS ICs by Body Current Injection
(2009)
Chen, Wen-Yi
;
Ker, Ming-Dou
;
Jou, Yeh-Ning
;
Huang, Yeh-Jen
;
Lin, Geeng-Lih
With the waffle layout style, body-injected technique implemented by body current injection on n-channel lateral DMOS (nLDMOS) has been successfully verified in a 0.5-mu m 16-V BCD process. The TIP measured results confirmed that the secondary breakdown current (I(t2)) of waffle nLDMOS can be significantly increased by the body current injection with the corresponding trigger circuit design. The latchup immunity of power-rail ESD protection circuit can be further improved by the stacked configuration with multiple nLDMOS devices in HV ICs.
Measurement on Snapback Holding Voltage of High-Voltage LDMOS for Latch-up Consideration
(2008)
Chen, Wen-Yi
;
Ker, Ming-Dou
;
Huang, Yeh-Jen
;
Jou, Yeh-Ning
;
Lin, Geeng-Lih
In high voltage (HV) ICs, the latch-up immunity of HV devices is often referred to the TLP-measured holding voltage because the huge power generated from DC curve tracer can easily damage HV device during measurement. An n-channel lateral DMOS (LDMOS) was fabricated in a 0.25-mu m 18-V bipolar CMOS DMOS (BCD) process to investigate the validity of TLP-measured snapback holding voltage to the device immunity against latch-up. Experimental results from curve tracer measurement and transient latch-up test show that 100-ns TLP underestimates the latch-up susceptibility of the 18-V LDMOS. By using the long-pulse TLP measurement, snapback holding voltage of the HV device has been found to degrade over time due to the self-heating effect. As a result, since the latch-up event is a reliability test with the time duration longer than millisecond, TLP measurement is not suitable for applying to investigate the snapback holding voltage of HV devices for latch-up.
Stacked Low-Voltage PMOS for High-Voltage ESD Protection with Latchup-Free Immunity
(2015)
Tang, Kai-Neng
;
Liao, Seian-Feng
;
Ker, Ming-Dou
;
Chiou, Hwa-Chyi
;
Huang, Yeh-Jen
Electrostatic discharge (ESD) and latchup are important reliability issues to the CMOS integrated circuits in high-voltage (HV) applications. In this work, the stacked low-voltage (LV) PMOS has been verified to sustain a high ESD level with high holding voltage in a 0.25-mu m BCD process. Stacked devices in different configuration were also investigated in silicon chip to get high ESD robustness and latchup-free immunity for HV applications.
The impact of high-voltage drift n-well and shallow trench isolation layouts on electrical characteristics of LDMOSFETs
(2007)
Huang, C. T.
;
Tsui, Bing-Yue
;
Liu, Hsu-Ju
;
Lin, Geeng-Lih
;
電子工程學系及電子研究所
The impact of the high-voltage drift n-well (HVNW) and shallow trench isolation (STI) regions on the electrical characteristics of 32V symmetry and asymmetry n-channel laterally diffused drain MOSFET (N-LDMOS) were evaluated. Asymmetry structure has higher threshold voltage owing to the transient enhancement diffusion (TED) of boron near source region. The smaller extension of the HVNW to STI (E(HVNW-STI) for asymmetry structure exhibits a wider safe-operating-area (SOA) from the hot-carrier reliability point of view. To obtain a higher on-current, the EHVNW-STI should be optimized because the steep sidewall of the STI may force current to flow through a longer distance in the HVNW. Finally, increase of EHVNW-STI cannot efficiently increase breakdown voltage.