Browsing by Author "Lin, Geng-Cing"

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A High-Performance Low V(MIN) 55nm 512Kb Disturb-Free 8T SRAM with Adaptive VVSS Control
(2011)
Yang, Hao-I
;
Yang, Shih-Chi
;
Hsia, Mao-Chih
;
Lin, Yung-Wei
;
Lin, Yi-Wei
This paper describes a high-performance low V(MIN) SRAM with a disturb-free 8T cell. The SRAM utilizes single-ended buffer Read, and cross-point data-aware Write Word-Line structure with adaptive VVSS control to eliminate Read disturb and Half-Select disturb, thus facilitating bit-interleaving architecture and achieving low V(MIN). A 512Kb test chip is implemented in UMC 55nm Standard Performance (SP) CMOS technology. The measurement results demonstrate operating frequency of 943MHz at 1.2V VDD and 209MHz at 0.6V VDD.
An All-Digital Bit Transistor Characterization Scheme for CMOS 6T SRAM Array
(2012)
Lin, Geng-Cing
;
Wang, Shao-Cheng
;
Lin, Yi-Wei
;
Tsai, Ming-Chien
;
Chuang, Ching-Te
We present an all-digital bit transistor characterization scheme for CMOS 6T SRAM array. The scheme employs an on-chip operational amplifier feedback loop to measure the individual threshold voltage (VTH) of 6T SRAM bit cell transistors (holding PMOS, pull-down NMOS, and access NMOS) in SRAM cell array environment. The measured voltage is converted to frequency with dual VCO and counter based digital read-out to facilitate data extraction, processing, and statistical analysis. A 512Kb test chip is implemented in 55nm 1P10M Standard Performance (SP) CMOS technology. Monte Carlo simulations indicate that the accuracy of the VTH measurement scheme is about 2-7mV at TT corner across temperature range from 85 degrees C to -45 degrees C, and post-layout simulations show the resolution of the digital read-out scheme is < 0.2mV per bit. Measured VTH distributions agree well with Monte Carlo simulation results.
Design and Implementation of Dynamic Word-Line Pulse Write Margin Monitor for SRAM
(2012)
Wang, Shao-Cheng
;
Lin, Geng-Cing
;
Lin, Yi-Wei
;
Tsai, Ming-Chien
;
Chiu, Yi-Wei
We present an all-digital monitor structure to measure the Write Margin (WM) with dynamic Word-Line (WL) pulse for standard CMOS 6T SRAM. Ring oscillator and frequency divider based structures are used to generate wide range WL pulses (150ps similar to 32ns) with resolution of 50ps. The bit-line voltage is then successively stepped down for dynamic Write Margin characterization under given word-line pulse width. An improved Skitter based structure is employed to measure the WL pulse width with resolution of 10 similar to 20ps. Implementation of a 256Kb test chip in UMC 55nm Standard Performance (SP) CMOS technology is described.
High-Performance 0.6V V-MIN 55nm 1.0Mb 6T SRAM with Adaptive BL Bleeder
(2012)
Yang, Hao-I
;
Lin, Yi-Wei
;
Hsia, Mao-Chih
;
Lin, Geng-Cing
;
Chang, Chi-Shin
This paper presents a 1.0Mb high-performance 0.6V V-MIN 6T SRAM design implemented in UMC 55nm Standard Performance (SP) CMOS technology. This design utilizes an adaptive LBL bleeder technique to reduce Read disturb and Half-Select disturb of 6T cells while maintaining adequate sensing margin. A bleeder timing control circuit adaptively adjusts the LBL voltage level prior to Read/Write operation to facilitate wide operation voltage range. Hierarchical WL, hierarchical BL, and distributed replica timing control scheme are used to improve SRAM performance. Based on measurement results, the SRAM operates from 1.5V down to 0.6V. The maximum operating frequency is 1.517GHz@1.5V and 469MHz@0.7V.