Browsing by Author "Lin, HC"

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A high-temperature thermodynamic model for metalorganic vapor phase epitaxial growth of InGaN
(1999-09-01)
Ou, J
;
Pan, YC
;
Lee, WH
;
Shu, CK
;
Lin, HC
A thermodynamic analysis tailored with a high-temperature parameter was performed for metalorganic vapor phase epitaxial (MOVPE) growth of InxGa1-xN alloys. Accordingly, a series of InGaN samples were prepared under various input In flow rates and growth temperatures. Theoretical results indicate that the In solid concentration tends to increase with increasing In flow rate and with decreasing temperature, whereas the metal droplets form more easily on the surface at lower growth temperatures and higher In fluxes, which are in good agreement with our experimental data.
A model for photoresist-induced charging damage in ultra-thin gate oxides
(1997)
Lin, HC
;
Chien, CH
;
Wang, MF
;
Huang, TY
;
Chang, CY
The role of photoresist (PR) in affecting the gate oxide damage during plasma processing boas reexamined in this work. if was observed that, during the O-2 plasma ashing, more severe antenna effect may occur in devices with PR covering. A model is proposed to explain this phenomenon. This model considers the ability of plasma current injection through the substrate contacts, which are hindered by PR covering, to adjust the potential difference between gate electrode and substrate. We Sound that the presence of PR, antenna ratio, and gate-oxide thickness are all important parameters for charging damage effect.
A novel methodology for extracting effective density-of-states in poly-Si thin-film transistors
(2004)
Lin, HC
;
Yeh, KL
;
Lee, MH
;
Su, YC
;
Huang, TY
A novel methodology that greatly simplifies the procedure of extracting the effective density-of-states (DOS) in polycrystalline-Si thin-film transistors (poly-Si TFTs) is proposed and demonstrated. The characterization is performed on a Schottky barrier (SB) TFT with electrical source/drain extensions induced by a field-plate. Only one single device and two simple subthreshold I-V measurements at room temperature are needed for full band-gap DOS extraction. Impacts of different process treatments are clearly resolved using this methodology.
A novel thin-film transistor with self-aligned field induced drain
(2001-01-01)
Lin, HC
;
Yu, CM
;
Lin, CY
;
Yeh, KL
;
Huang, TY
In this letter, a novel thin-film transistor with a self-aligned field-induced-drain (SAFID) structure is reported for the first time. The new SAFID TFT features a self-aligned sidewall spacer located on top of the drain offset region to set its effective length, and a bottom gate (or field plate) situated under the drain offset region to electrically induce the field-induced-drain (FID). So, unlike the conventional off-set-gated TFTs with their effective FID length set by two separate photolithographic masking layers, the new SAFID is totally immune to photomasking misalignment errors, while enjoying the low off-state leakage as well as high turn-on characteristics inherent in the FID structure. Polycrystalline silicon TFTs with the new SAFID structure have been successfully fabricated with significant improvement in the on/off current ratio.
A simple and low-cost method to fabricate TFTs with poly-Si nanowire channel
(2005-09-01)
Lin, HC
;
Lee, MH
;
Su, CJ
;
Huang, TY
;
Lee, CC
A very simple and low-cost scheme is proposed for fabricating thin-film transistors with poly-Si nanowire (NW) channels. In this scheme, the poly-Si NW channel is formed by cleverly employing the poly-Si sidewall spacer technique. In addition, the poly-Si NW channel is genuinely exposed to the environment after the poly-Si sidewall spacer formation in the new scheme. This unique feature, together with its simplicity and low-cost, makes this approach very suitable for applications and manufacturing of bio-logic sensing devices. Good device performance is demonstrated in this letter.
A study on the radiation hardness of flash cell with horn-shaped floating-gate
(1997-09-01)
Huang, TY
;
Jong, FC
;
Chao, TS
;
Lin, HC
;
Leu, LY
The effects of radiation on the characteristics of split-gate electrical erasable programmable read only memory (EEPROM)/flash cells with recently-proposed horn-shaped floating gates are studied in terms of cell read current; data retention, cycling endurance, program/erase efficiency, threshold voltage and junction leakage. Our results show that the cells appear to survive after 1 Mrad (Si) Co-60 irradiation. Moreover, the after-irradiation cell read current actually increases in the ''erase'' (i.e., low-threshold voltage, high-conducting) state (i.e., improves), albeit the cell read current also increases in the ''program'' (i.e., high-threshold voltage, low-conducting) state (i.e., a degradation). Our results also show that, despite an improvement in the initial read current in the ''erase'' state immediately after radiation, the write/erase cycling endurance of the flash cells is significantly impeded after irradiation, due to a much faster ''window closure'' rate in the ''erase'' state, although the cell read current is found to remain relatively stable in the ''program'' state after cycling.
A study on the radiation hardness of flash cell with horn-shaped floating-gate
(1997-09-01)
Huang, TY
;
Jong, FC
;
Chao, TS
;
Lin, HC
;
Leu, LY
The effects of radiation on the characteristics of split-gate electrical erasable programmable read only memory (EEPROM)/flash cells with recently-proposed horn-shaped floating gates are studied in terms of cell read current; data retention, cycling endurance, program/erase efficiency, threshold voltage and junction leakage. Our results show that the cells appear to survive after 1 Mrad (Si) Co-60 irradiation. Moreover, the after-irradiation cell read current actually increases in the ''erase'' (i.e., low-threshold voltage, high-conducting) state (i.e., improves), albeit the cell read current also increases in the ''program'' (i.e., high-threshold voltage, low-conducting) state (i.e., a degradation). Our results also show that, despite an improvement in the initial read current in the ''erase'' state immediately after radiation, the write/erase cycling endurance of the flash cells is significantly impeded after irradiation, due to a much faster ''window closure'' rate in the ''erase'' state, although the cell read current is found to remain relatively stable in the ''program'' state after cycling.
Ambipolar Schottky barrier silicon-on-insulator metal-oxide-semiconductor transistors
(2003-02-01)
Lin, HC
;
Wang, MF
;
Lu, CY
;
Huang, TY
;
電子工程學系及電子研究所
A novel Schottky barrier silicon-on-insulator metal-oxide-semiconductor field-effect transistor featuring metallic source/drain and an electrical drain junction has been fabricated and characterized. The formation of electrical drain junction, or the field-induced drain (FID), is controlled by a metal field-plate overlying the passivation oxide. Excellent ambipolar operation is demonstrated on the device. Specifically, on/off current ratios up to 10(8) and 10(7) are observed for p- and n-channel operations, respectively. Meanwhile, the off-state leakage current shows very weak dependence on the voltage difference between the main-gate and the drain, highlighting the effectiveness of FID. Finally, negative differential conductance effect is observed for n-channel operation, which is identified as due to dynamic hot electron trapping during device characterization. (C) 2002 Elsevier Science Ltd. All rights reserved.
Ambipolar Schottky-barrier TFTs
(2002-02-01)
Lin, HC
;
Yeh, KL
;
Huang, TY
;
Huang, RG
;
Sze, SM
A novel Schottky-barrier metal-oxide-semiconductor thin-film transistor (SBTFT) was successfully demonstrated and characterized. The new SBTFT device features a fleld-induced-drain (FID) region, which is controlled by a metal field-plate lying on top of the passivation oxide. The FED region is sandwiched between the silicided drain and the active channel region. Carrier types and the conductivity of the transistor are controlled by the metal field-plate. The device is thus capable of ambipolar operation. Excellent ambipolar performance with on/off current ratios over 10(6) for both p- and n-channel operations was realized simultaneously on the same device fabricated with polysilicon active layer. Moreover, the off-state leakage current shows very weak dependence on the gate-to-drain voltage difference with the FID structure. Finally, the effects of FED length are explored.
An elucidation of solid incorporation of InGaN grown by metalorganic vapor phase epitaxy
(1998-06-01)
Ou, J
;
Chen, WK
;
Lin, HC
;
Pan, YC
;
Lee, MC
We carried out a systematic study on the solid incorporation of InGaN under various growth conditions using metalorganic vapor phase epitaxy (MOVPE). The solid distribution of InGaN was found to be very sensitive to the growth temperature, and the TMGa and TMIn flow rates. Experimental results indicated that at low Ga flow rates InGaN growth is essentially governed by thermodynamic factors, whereas at high growth rate the InGaN solid concentration is determined merely by the vapor composition in the gas phase. In regard to the effect of TMIn flow rates on InGaN growth, it was found that once In droplets form on the surface, the In growth efficiency correspondingly decreases significantly; accounting for the low In solid concentration in InGaN at high TMIn flow rates.
Application of field-induced source/drain Schottky metal-oxide-semiconductor to fin-like body field-effect transistor
(2002-06-01)
Lin, HC
;
Wang, MF
;
Hou, FJ
;
Liu, JT
;
Huang, TY
A novel Schottky barrier silicon-on-insulator (SOI) metal-oxide-semiconductor field effect transistor (MOSFET) device was proposed and demonstrated, The new device features a silicide source/drain and field-induced source/drain (S/D) extensions. Excellent ambipolar performance with a near-ideal sub-threshold slope (similar to 60 mV/decade) and high on-/off-state current ratio (comparable to or higher than 10(9)) is realized, for the first time, on a single device. These encouraging results suggest that the new device may be suitable for some niche applications requiring simple and low-temperature processing of complementary metal-oxide-semiconductor(CMOS)-like devices.
Breakdown characteristics of ultra-thin gate oxides caused by plasma charging
(1999)
Chen, CC
;
Lin, HC
;
Chang, CY
;
Chien, CH
;
Huang, TY
Breakdown characteristics of ultra-thin gate oxides caused by plasma charging were studied in this work. It is observed that as oxide thickness is scaled down to 4 nn, some traditional monitor parameters may lose their sensitivity for detecting oxide degradation induced by plasma charging damage, due to insignificant trap generation. Even the gate leakage current, although sensitive for 4 nm oxide, may no longer be sensitive enough for even thinner oxide (e.g., 2.6 nm), due to the existence of large tunneling current. Moreover, several soft-breakdown events were found to occur in ultrathin oxide before the final onset of a catastrophic hard-breakdown. Finally, an equivalent local oxide thickness is calculated using local oxide thinning model to estimate the stepwise increase of gate current after soft-breakdown event.
Breakdown modes and their evolution in ultrathin gate oxide
(2002-10-01)
Lin, HC
;
Lee, DY
;
Huang, TY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Post-breakdown current-voltage characteristics of metal-oxide-semiconductor (MOS) devices kith an ultrathin gate oxide layer have been carefully studied. Several breakdown modes were identified. Specifically, it was found that the typical soft-breakdown mode induced in an oxide lay er thinner than 3 nm is actually quite different from that in an oxide layer thicker than 3 nm. Based on these findings, we have also proposed a model to explain the evolution of different breakdown modes. The model takes into consideration the thermal runaway process at the breakdown moment, and is substantiated by a number of experimental findings. Impacts of each breakdown mode on device switching behavior are also discussed.
Channel backscattering characteristics of strained PMOSFETs with embedded SiGe source/drain
(2005)
Lin, HN
;
Chen, HW
;
Ko, CH
;
Ge, CH
;
Lin, HC
Channel backscattering ratios of PMOSFETs with various embedded SiGe source/drain structures are analyzed in terms of the scattering theory We found that both the backscattering ratio and injection velocity are greatly influenced by the location and recess depth of SiGe source/drain. Although the strain-enhanced injection velocity is beneficial to the current gain, the accompanying backscattering ratio increase adversely impacts the overall performance, and therefore a trade-off exists between injection velocity and backscattering ratio during the optimization of such strain technique. The mechanism of increased backscattering ratio under uniaxial compressive strain is also investigated.
Channel backscattering characteristics of uniaxially strained nanoscale CMOSFETs
(2005-09-01)
Lin, HN
;
Chen, HW
;
Ko, CH
;
Ge, CH
;
Lin, HC
Channel backscattering characteristics of uniaxially strained nanoscale CMOSFETs are reported for the first time. Channel backscattering ratio increases and decreases under uniaxial tensile and compressive strain, respectively. It is found that in sub-100-nm devices, strain-induced modulation of carrier mean-free path for backscattering and reduction in kBT layer thickness are responsible for the different behaviors of backscattering ratio. Nevertheless, the source-side injection velocity improves irrespective of the strain polarities. The impact of channel backscattering ratio on drive current is also analyzed in terms,of ballistic efficiency and injection velocity.
Characteristics of polycrystalline silicon thin-film transistors with electrical source/drain extensions induced by a bottom sub-gate
(2002-05-01)
Yu, M
;
Lin, HC
;
Chen, GH
;
Huang, TY
;
Lei, TF
Characteristics of polycrystalline silicon thin-film transistors (TFT) with source/drain extensions induced by a bottom sub-gate were explored, high on/off current ratio up to 10(7) could be achieved for both n- and p-channel devices. Nevertheless, the performance is significantly degraded by a marked increase of off-state leak-age current when the channel length is scaled below 1 mum. Moreover, a hump in the subthreshold current-voltage regime is observed. After careful analysis, it is found that the leakage current is strongly dependent on the field strength and is not a thermally activated process. A leakage path along the bottom interface of the poly-Si channel layer is proposed to explain these results.
Characteristics of Schottky barrier poly-Si thin film transistors with excimer laser annealing treatment
(2003)
Yeh, KL
;
Lin, HC
;
Tsai, RW
;
Lee, MH
;
Huang, TY
Poly-Si Schottky barrier poly-Si thin-film transistors (SB TFT) with field-induced drain (FID) have recently been demonstrated. Such devices exhibit ambipolar operation capability with low off-state leakage current. In this study, we investigate and compare the characteristics of poly-Si SB TFTs with channel layer prepared by either excimer laser crystallization (ELC) or solid-phase crystallization (SPC) method. It is shown that the use of ELC could greatly improve the device characteristics compared to the SPC counterparts. Excellent device performance in terms of steep subthreshold slope and high on/off current ratio (>10(8)) for both p- and n-channel operations are demonstrated on a single device with ELC channel. The effects of sub-gate bias, channel length, and offset channel length, on device characteristics are also explored.
Characterization of antenna effect by nondestructive gate current measurement
(1996-08-15)
Lin, HC
;
Chien, CH
;
Huang, TY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A novel method is proposed for the effective characterization of plasma-charge-induced damage on thin gate oxides. We have found that the gate current measured at V-g(gate voltage) = V-th(threshold voltage) under a low drain bias (e.g., 0.1 V) is a good indicator of the damage. Since the proposed method requires only low bias voltages, it does not cause additional damage to the devices. The proposed gate current measurement is also easy to incorporate to device measurement routines without an extra stressing step, and thus provides a simple and efficient damage indicator for studying plasma-charge-induced damage.
Characterization of antenna effect by nondestructive gate current measurement
(1996-08-15)
Lin, HC
;
Chien, CH
;
Huang, TY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A novel method is proposed for the effective characterization of plasma-charge-induced damage on thin gate oxides. We have found that the gate current measured at V-g(gate voltage) = V-th(threshold voltage) under a low drain bias (e.g., 0.1 V) is a good indicator of the damage. Since the proposed method requires only low bias voltages, it does not cause additional damage to the devices. The proposed gate current measurement is also easy to incorporate to device measurement routines without an extra stressing step, and thus provides a simple and efficient damage indicator for studying plasma-charge-induced damage.
Charge pumping profiling technique for the evaluation of plasma-charging-enhanced hot-carrier effect in short-N-channel metal-oxide-semiconductor field-effect transistors
(2002-07-01)
Chen, SJ
;
Chung, SSS
;
Lin, HC
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Plasma etching of poly-silicon in a metal-oxide-semiconductor field-effect transistor (MOSFET) during the gate definition process induces edge damage at the gate-drain overlap edge. This edge damage will be further enhanced by the antenna effect and cause a more serious hot-carrier (HC) effect, particularly in short-channel devices. We call this phenomenon the plasma-charging-enhanced HC effect. In this paper, this plasma-charging-enhanced HC effect is evaluated by the charge pumping (CP) profiling technique, in which the enhanced damage at the gate-drain overlap gate oxide region can be identified. A three-phase plasma damage mechanism is then proposed to explain the observed effect. According to experimental results, it was shown that the interface traps generated at the gate-drain overlap edge are mainly attributed to the plasma-charging-enhanced HC effect. These interface traps (Nit) become the dominant mechanism of the drain current (ID) degradation, which increases with a reducing channel length (L). Again, the enhanced HC-effect-induced-degradation will dominate the device reliability under long-term operations.