Browsing by Author "Lin, HS"

Now showing 1 - 3 of 3

A new insight into the degradation mechanisms of various mobility-enhanced CMOS devices with different substrate engineering
(2005)
Chung, SS
;
Liu, YR
;
Wu, SJ
;
Lai, CS
;
Liu, YC
In this paper, the difference in degradation mechanism for different substrate engineered CMOS devices has been reported for the first time. These two different substrate engineering includes hybrid substrate engineering, with (100) and (110) orientations, and strained-Si devices. Different mechanisms are responsible for these two different mobility enhancement schemes. For strained-Si devices, it shows that the dominant mechanism for HC(Hot Carrier) and NBT (Negative Bias Temperature) degradations is attributed to the lateral electric field resulting from the mobility enhancement. While for (110)/(100) substrate engineered devices, the dominant mechanism is due to the dangling bond of the surface. In other words, for (I I 0)/(l 00) substrate, the device degradation is weakly dependent on the mobility enhancement while largely dependent on the bond strength. Finally, the difference in temperature dependence of HC and NBT has also been observed for both strained-Si and (110)/(100) substrate devices. Sophisticated measurement techniques, charge pumping (CP) and gated-diode (GD) measurement, have been employed to understand these device mechanisms. These results provide a guideline for the device design and the understanding of related reliabilities in the popular strained-Si and hybrid substrate technology CMOS devices.
A novel and direct determination of the interface traps in sub-100nm CMOS devices with direct tunneling regime (12 similar to 16A) gate oxide
(2002)
Chung, SS
;
Chen, SJ
;
Yang, CK
;
Cheng, SM
;
Lin, SH
For the first time, an improved charge pumping (CP) method has been implemented for direct determination of the interface traps in ultra-short gate length CMOS devices with ultra-thin gate oxide in the direct tunneling regime. The leakage current in a 12-16A gate oxide can be removed from the measured CP current, which enables accurate determination of the interface traps. This method has, been demonstrated successfully for various RTNO grown and RPN treated oxide CMOS devices with very thin gate oxide. Moreover, it can be used as a good monitor of ultra-thin gate oxide process and the evaluations of device reliabilities in relating to the interface trap generation.
Virtual integration and profitability: some evidence from Taiwan's IC industry
(2005)
Chu, PY
;
Teng, MJ
;
Huang, CH
;
Lin, HS
;
管理科學系
Taiwan's Integrated Circuit (IC) industry is of particular interest due to its increasing global importance and its unique, virtually integrated infrastructure. This study was conducted to examine the strategy-performance consequences of strategic group membership and attempted empirically to investigate the relationship between the profitability of Taiwan's IC firms (dependent variables) and both firms' business strategies (virtual integration versus IDM) and industrial business cycles (contingent variable). Data was taken from the Taiwan's Integrated Circuit industry for the period 1994-2001. Significant and interesting results were obtained. First, the main factor of business models significantly affects a firm's profitability and the variation over time. Secondly, the significance of the effect of the business models was still found when the variable of business cycle was included. It implied that the effectiveness of virtual integration to increase a firm's return on assets and return on equity existed at any stage of business cycles. An increasing number of independent IC design firms worldwide seem to support the findings of this study. However, the IDM firms may still exist due to their strategic commitment though the virtually integrated firms have higher profitability.