Browsing by Author "Lin, Hsiao-Yi"

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A reliability model for low-temperature polycrystalline silicon thin-film transistors
(2007-05-01)
Chen, Chih-Yang
;
Lee, Jam-Wem
;
Lee, Po-Hao
;
Chen, Wei-Cheng
;
Lin, Hsiao-Yi
We proposed here a reliability model that successfully. introduces both the physical mechanisms of negative bias temperature instability (NBTI) and hot carrier stress (HCS) for p-channel low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs). The proposed model is highly matched with the experimental results, in which the NBTI dominates the device reliability at small negative drain bias while the HCS dominates the degradation at large negative drain bias. In summary, the proposed model provides a comprehensive way to predict the lifetime of the p-channel LTPS TFTs, which is especially necessary for the system-on-panel circuitry design.
Analysis of negative bias temperature instability in body-tied low-temperature polycrystalline silicon thin-film transistors
(2008-02-01)
Chen, Chih-Yang
;
Ma, Ming-Wen
;
Chen, Wei-Cheng
;
Lin, Hsiao-Yi
;
Yeh, Kuan-Lin
Negative bias temperature instability (NBTI) degradation mechanism in body-tied low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs) is analyzed by the charge-pumping (CP) technique. The properties of bulk trap states (including interface and grain boundary trap states) are directly characterized from the CP current. The increase of the fixed oxide charges is also extracted, which has not been quantified in previous studies of NBTI degradation in LTPS TFTs. The experimental results confirm that the NBTI degradation in LTPS TFTs is caused by the generation of bulk trap states and oxide trap states.
Bias temperature instabilities for low-temperature polycrystalline silicon complementary thin-film transistors
(2007)
Chen, Chih-Yang
;
Lee, Jam-Wem
;
Ma, Ming-Wen
;
Chen, Wei-Cheng
;
Lin, Hsiao-Yi
The degradation mechanisms of both negative bias temperature instability (NBTI) and positive bias temperature instability (PBTI) were studied for low-temperature polycrystalline silicon complementary thin-film transistors. Measurements show that both NBTI and PBTI are highly bias dependent; however, the effect of the temperature is only functional on the NBTI stress. Furthermore, instead of interfacial trap-state generation during the NBTI stress, the PBTI stress passivates the interface trap states. We conclude that the diffusion-controlled electrochemical reactions dominate the NBTI degradation while charge trapping in the gate dielectric controls the PBTI degradation. (c) 2007 The Electrochemical Society.
Characterization of nitride hole lateral transport in a charge trap flash memory by using a random telegraph signal method
(2017-07-17)
Liu, Yu-Heng
;
Jiang, Cheng-Min
;
Lin, Hsiao-Yi
;
Wang, Tahui
;
Tsai, Wen-Jer
We use a random telegraph signal method to investigate nitride trapped hole lateral transport in a charge trap flash memory. The concept of this method is to utilize an interface oxide trap and its associated random telegraph signal as an internal probe to detect a local channel potential change resulting from nitride charge lateral movement. We apply different voltages to the drain of a memory cell and vary a bake temperature in retention to study the electric field and temperature dependence of hole lateral movement in a nitride. Thermal energy absorption by trapped holes in lateral transport is characterized. Mechanisms of hole lateral transport in retention are investigated. From the measured and modeled results, we find that thermally assisted trap-to-band tunneling is a major trapped hole emission mechanism in nitride hole lateral transport. Published by AIP Publishing.
Dynamic negative bias temperature instability in low-temperature poly-Si thin-film transistors
(2007)
Chen, Chih-Yang
;
Wang, Tong-Yi
;
Ma, Ming-Wen
;
Chen, Wei-Cheng
;
Lin, Hsiao-Yi
Dynamic negative bias temperature instability in p-channel low-temperature poly-Si thin-film transistors was studied in this paper. The degradation of the devices was found to be voltage and temperature dependent. In addition, the frequency and duty ratio of the gate pulse affects the degree of the device degradation. The mechanism of the device degradation was investigated, and a physical model is proposed to explain the mechanism.
High-Performance Poly-Si TFTs of Top-Gate with High-kappa Metal-Gate Combine the Laser Annealed Channel and Glass Substrate
(2011)
Lu, Yi-Hsien
;
Chien, Chao-Hsin
;
Kuo, Po-Yi
;
Yang, Ming-Jui
;
Lin, Hsiao-Yi
We demonstrate high-performance low-temperature poly-Si thin film transistors (LTPS-TFTs) with a TaN/Hf-based top-gate-stack and combine the channel film by laser annealing and glass substrate (glass substrate high-kappa metal-gate thin film transistor, called GSHM-TFTs). The GSHM-TFTs of n-channel (called GSHM-NTFTs) exhibit a very low threshold voltage, low supply voltage (similar to 2 V), steep subthreshold swing (S.S.) similar to 95 mV/dec, and high I(ON)/I(OFF) ratio >10(7). In contrast, GSHM-TFTs of p-channel (called GSHM-PTFTs) exhibit an S.S. similar to 154 mV/dec and an I(ON)/I(OFF) ratio even higher than 10(8). Furthermore, the driving currents are also enhanced in GSHM-TFTs. These significant improvements are due to the combination of laser annealed channel film and the very high gate-capacitance density provided by HfO(2) gate dielectrics with the effective oxide thickness of 14 nm. (C) 2010 The Electrochemical Society. [DOI: 10.1149/1.3504147] All rights reserved.
Plasma damage-enhanced negative bias temperature instability in low-temperature polycrystalline silicon thin-film transistors
(2006-11-01)
Chen, Chih-Yang
;
Lee, Jam-Wem
;
Chen, Wei-g Chen
;
Lin, Hsiao-Yi
;
Yeh, Kuan-Lin
In this letter, a mechanism that will make negative bias temperature instability (NBTI) be accelerated by plasma damage in low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs) is presented. The experimental results confirm that the mechanism, traditionally found in the thin gate-oxide devices, does exist also in UPS TFTs. That is, when performing the NBTI measurement, the UPS TFTs with a larger antenna ratio will have a higher degree in degradation of the threshold voltage, effective mobility, and drive current under NBTI stress. By extracting the related device parameters, it was demonstrated that the enhancement is mainly attributed to the plasma-damage-modulated creating of interfacial states, grain boundary trap states, and fixed oxide charges. It could be concluded that plasma damage will speed up the NBTI and should be avoided for the UPS TFT circuitry design.
Plasma-induced damage on the performance and reliability of low-temperature polycrystalline silicon thin-film transistors
(2007)
Chen, Chih-Yang
;
Wang, Shen-De
;
Shieh, Ming-Shan
;
Chen, Wei-Cheng
;
Lin, Hsiao-Yi
We have investigated the impact of plasma-induced damage on the performance and reliability of low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs). The LTPS TFTs having different antenna structures were used to study the effects of the plasma-etching process. We observed that performance instability occurred for the devices having a relatively large-area antenna. Plasma damage mainly caused nonuniform distribution of the threshold voltages in the LTPS TFTs, presumably because of charge trapping in the gate dielectric during the plasma-etching process. The reliabilities of the LTPS TFTs having larger antenna areas were found to be more degraded under gate-bias stress and hot-carrier stress than those of the samples having smaller antenna areas. Because of their enhanced plasma damage, we speculate that the LTPS TFTs having larger antenna areas possess more trap states in the gate dielectrics. During gate-bias stress or hot-carrier stress, therefore, charges can be injected into the gate dielectric through trap-assisted tunneling, resulting in significant degradation of both the performance and reliability. (c) 2006 The Electrochemical Society.
Process induced instability and reliability issues in low temperature poly-Si thin film transistors
(2006)
Chen, Chih-Yang
;
Wang, Shen-De
;
Shieh, Ming-Shan
;
Chen, Wei-Cheng
;
Lin, Hsiao-Yi
We investigated the impact of plasma process on the devices' performance and reliability degradation of low temperature poly-Si thin film transistors (LTPS TFTs). LTPS TFTs with different antenna areas were used to study the effects of the plasma etching process on the devices. The larger TFT antenna area, the more performance instability occurs. The reliability of LTPS TFTs with large antenna areas was found to be degraded from gate bias stress and hot carrier stress.