Browsing by Author "Lin, Jian-He"

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A Digital Low-Dropout-Regulator with Steady-State Load Current (SLC) Estimator and Dynamic Gain Scaling (DGS) Control
(2016)
Lin, Jian-He
;
Tsou, Wen-Jie
;
Chen, Ke-Horng
;
Wey, Chin-Long
;
Lin, Ying-Hsi
conventional digital low dropout (D-LDO) regulator usually suffers from the drawback of long settling time during transient response due to the usage of shift register architecture. In this paper, the proposed D-LDO regulator can observe the output voltage variations during load transient time to predict the load current for fast transient response. Near optimum turn on power MOSFET in steady state can be derived by the proposed steady-state load current (SLC) estimator while the dynamic gain scaling (DGS) technique can improve transient response and avoid limiting cycle oscillation (LCO) problem. Test chip was designed in 0.18 mu m CMOS process. Simulation results showed the transient response time can be reduced by 88% from 920ns to 115ns.
A DVS-Based Burst Mode with Automatic Entrance Point Control Technique in DC-DC Boost Converter for Wearable Devices and IoT Applications
(2017-01-01)
Cheng, Chiao-Hung
;
Lin, Li-Chi
;
Lin, Jian-He
;
Chen, Ke-Horng
;
Lin, Ying-Hsi
the proposed dynamic voltage scaling (DVS) based burst mode links the DVS technique in a system on a chip (SoC) and the burst mode operation of the DC-DC converter for further efficiency improving. Conventional burst mode has only one entrance transition point (ETP) between the pulse width modulation (PWM) and the burst mode, so the voltage ripple is high at low DVS voltage while the efficiency is low at high DVS voltage. The proposed DVS-based burst mode uses the automatic entrance point control (AEPC) technique to decide multiple ETP values corresponding to the voltage identification (VID) code from the SoC. The quality enhancement technique deliberately adjusts the burst reference voltage to further reduce the output ripple with acceptable loss of efficiency. The tested DC-DC boost converter with the DVS-based burst mode technique is fabricated in 0.18 mu m CMOS process. Measurement results show that the efficiency is higher than 85% when the output voltage varies from 1.8V to 3.2V (controlled by the DVS) and load current ranges from 0.1mA to 140mA, with peak efficiency 94%.
A High Efficiency and Fast Transient Digital Low-Dropout Regulator With the Burst Mode Corresponding to the Power-Saving Modes of DC-DC Switching Converters
(2020-04-01)
Lin, Jian-He
;
Yang, Shang-Hsien
;
Muniandi, Balakumar
;
Ma, Yu-Sheng
;
Huang, Chia-Ming
The proposed digital low-dropout regulator uses nonlinear switching control (NLSC) technique to suppress voltage ripple to less than 6mV when the switching noise voltage of a switching regulator operating in a power-saving mode is greater than 50mV. In addition, the NLSC technique improves the current efficiency by reducing the quiescent current to less than 10 A and reduces the switching power loss through variable switching frequency control. With a load step of 1-20mA, the transient response time is 1.3 s and the peak current efficiency is 99.8 at heavy loads.
A High-Efficiency and Fast-Transient Digital-Low-Dropout Regulator with the Burst Mode Corresponding to the Power-Saving Modes of DC-DC Switching Converters
(2018-01-01)
Lin, Jian-He
;
Ma, Yu-Sheng
;
Huang, Chia-Ming
;
Lin, Li-Chi
;
Cheng, Chiao-Hung
A High-Efficiency and Fast-Transient Digital-Low-Dropout Regulator with the Burst Mode Corresponding to the Power-Saving Modes of DC-DC Switching Converters
(2018-01-01)
Lin, Jian-He
;
Ma, Yu-Sheng
;
Huang, Chia-Ming
;
Lin, Li-Chi
;
Cheng, Chiao-Hung
Digital Low-Dropout Regulator with Anti PVT-Variation Technique for Dynamic Voltage Scaling and Adaptive Voltage Scaling Multicore Processor
(2017-01-01)
Tsou, Wen-Jie
;
Yang, Wen-Hau
;
Lin, Jian-He
;
Chen, Hsin
;
Chen, Ke-Horng