Browsing by Author "Lin, Jian-Ru"

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120V/ns Output Slew Rate Enhancement Technique and High Voltage Clamping Circuit in High Integrated Gate Driver for Power GaN FETs
(2015)
Yang, Hsiang-An
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Chiu, Chao-Chang
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Lai, Shin-Chi
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Chen, Jui-Lung
;
Chang, Chih-Wei
High power density is a key point that power converters endeavor to pursue. However, it is rare that gate driver of power converter can switch under high supply voltage with a fast operation frequency. In this paper, a half-bridge driver with the slew rate enhancement (SRE) technique is proposed and its switching frequency can be increased to 25MHz under a 700V supply voltage. Besides, the proposed high voltage clamping circuit ensures all circuits operating in a safe region without any overvoltage problems in the bootstrap operation. With specifically developed high voltage high speed (HVHS) process, high-side and low-side circuits can be well shielded by the isolation well which is embedded in the level shifter device to minimize chip size.
200nA Low Quiescent Current Deep-Standby Mode in 28nm DC-DC Buck Converter for Active Implantable Medical Devices
(2015)
Chu, Li-Cheng
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Yang, Te-Fu
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Huang, Ru-Yu
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Su, Yi-Ping
;
Lin, Chiun-He
the proposed deep-standby mode (DSM) is used in 28nm power management unit (PMU) for long-term usage in active implantable medical devices (AIMD). The PMU can upgrade its normal mode with the proposed embedded auto-cancellation (EAC) technique in order to have high accuracy even if the battery is aging and the PVT variations occur. The test chip fabricated in 28nm CMOS process features low quiescent current of 200nA and output voltage accuracy of 98%. Seamless transition among the DSM and the accurate mode demonstrates both low quiescent current and high accuracy can be achieved in the proposed PMU.
90% Peak Efficiency Single-Inductor-Multiple-Output DC-DC Buck Converter with Output Independent Gate Drive Control
(2015-01-01)
Su, Yi-Ping
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Lin, Chiun-He
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Peng, Shen-Yu
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Huang, Ru-Yu
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Yang, Te-Fu
93% Efficiency and 0.99 Power Factor in Pseudo-linear LED Driver
(2016-01-01)
Chiu, Shao-Wei
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Kuo, Chun-Chieh
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Chuang, Kai-Cheng
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Yang, Wen-Hau
;
Chen, Ke-Horng
The proposed pseudo-linear LED driver can effectively solve the serious flicker in conventional linear LED driver (LLD). Besides, it has good electromagnetic interference (EMI) performance similar to that in conventional LLD at high AC input voltage. In the meanwhile, it has high power factor (PF) similar to boost switching regulator (SWR) LED driver at low AC input voltage. Furthermore, owing to the combination of line filter and the active full bridge rectifier, the pseudo-linear LED driver has a compact solution and high efficiency. The test chip was fabricated in 0.5 mu m 500V LDMOS process. Experimental results show 93% high efficiency, 6% total harmonic distortion (THD), and 0.99 PF at the power of 7W.
95% Light-load Efficiency Single-Inductor Dual-Output DC-DC Buck Converter with Synthesized Waveform Control Technique for USB Type-C
(2016)
Yang, Wen-Hau
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Lin, Chiun-He
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Chen, Ke-Horng
;
Wey, Chin-Long
;
Lin, Ying-Hsi
The proposed single-inductor dual-output (SIDO) converter can provide wide range in duty ratio control to convert input voltage 520V to dual output voltages 3.3V and 1.2V when its switching frequency is raised to 10MHz for compact size solution. The proposed synthesized waveform control (SWC) technique can emulate the inductor current without being affected by switching noise. Thus, the minimum allowable duty ratio can be lowered to 6% to meet the requirement of USB-C in one-stage low duty ratio conversion. Moreover, the switching frequency is dynamically decreased by the derived DC loading information from the SWC technique. Not only the output power MOSFET but also the main power MOSFET switch in a load-dependent switching frequency for power saving. 67% more power reduction can be obtained. 95% and 83% efficiency are achieved at light and heavy loads, respectively, when the silicon is limited within 1400 mu m*1350 mu m.
99% High Accuracy Knee Voltage Detection for Primary-side Control in Flyback Converter
(2015)
Tsai, Tsung-Hsun
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Chen, Ke-Horng
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Tsai, Tsung-Yen
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Lin, Jian-Ru
;
Lin, Ying-Hsi
this paper proposed the adaptive knee voltage detection (KVD) technique to improve the output voltage accuracy of the primary side regulator. Owing to the insertion of the snubber circuit for reducing overshoot voltage, conventional KVD technique fails to get the output voltage information and thus to deteriorate the output voltage accuracy. Analysis of the snubber circuit and the resonance of the primary side can determine the band-pass filter in the proposed AKVD technique to get high accuracy output information without being affected by any kinds of resonances. Test chip designed in VIS 0.5 mu m BCD process demonstrates the accuracy of the output voltage higher than 99%. Besides, any abnormal detection won\'t happen and thus the output ripple can be kept low.
A 20MHz Low Dropout Controlled Current Sensor for Constant On-Time Based Envelop Tacking Supply Modulator for Radio Frequency Power Amplifier
(2018-01-01)
Lin, Wei-Ting
;
Lin, Zong-Yi
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Liu, Chia-Hao
;
Chen, Ke-Horng
;
Lin, Ying-Hsi
this paper presents a LDO-controlled current sensor for accelerating constant on-time (COT) switching regulators (SWRs) for high efficiency envelope tracking power modulators (ETSMs) for RF power amplifiers (RF PAs). The proposed LDO-controlled current sensor controls the feedback loop of the SWR, rather than the traditional current sensing technique, in the case of fast envelope tracking. The LDO regulator behaves as the master to rapidly trigger the SWR as a slave energy provider to rapidly deliver the average energy to the RF PA for high efficiency. The experimental results show that the test chip fabricated in 0.18 mu m CMOS process can accurately track the RF envelope signal, and the peak efficiency is 86.7% when the power is 0.95W.
A 96%-Efficiency and 0.5%-Current-CrossRegulation Single-Inductor Multiple Floating-Output LED Driver with 24b Color Resolution
(2016)
Yang, Hsiang-An
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Yang, Wen-Hau
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Chen, Ke-Horng
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Wey, Chin-Long
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Lin, Ying-Hsi
A Digital Low-Dropout-Regulator with Steady-State Load Current (SLC) Estimator and Dynamic Gain Scaling (DGS) Control
(2016)
Lin, Jian-He
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Tsou, Wen-Jie
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Chen, Ke-Horng
;
Wey, Chin-Long
;
Lin, Ying-Hsi
conventional digital low dropout (D-LDO) regulator usually suffers from the drawback of long settling time during transient response due to the usage of shift register architecture. In this paper, the proposed D-LDO regulator can observe the output voltage variations during load transient time to predict the load current for fast transient response. Near optimum turn on power MOSFET in steady state can be derived by the proposed steady-state load current (SLC) estimator while the dynamic gain scaling (DGS) technique can improve transient response and avoid limiting cycle oscillation (LCO) problem. Test chip was designed in 0.18 mu m CMOS process. Simulation results showed the transient response time can be reduced by 88% from 920ns to 115ns.
A Direct AC-DC and DC-DC Cross-Source Energy Harvesting Circuit with Analog Iterating-Based MPPT Technique with 72.5% Conversion Efficiency and 94.6% Tracking Efficiency
(2016-08)
Chen, Shin-Hao
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Huang, Tzu-Chi
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Ng, Shao Siang
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Lin, Kuei-Liang
;
Du, Ming-Jhe
The proposed cross-source energy (CSE) harvesting system accepts universal energy sources, including the ac and dc sources. The buck-boost conversion of CSE automatically converts ac or dc input into dc output without being limited by the type of universal energy source. The CSE technique simultaneously supplies the regulated output for the system loading and the battery charging output. A test chip fabricated in the VIS Bipolar, CMOS, and DMOS (BCD) process can optimally derive harvest energy with 72.5% power efficiency when one solar input source is used. A backup converter is designed to complement the CSE technique to guarantee the regulation of output voltage. The proposed analog iterating-based (AIB) maximum power point tracking (MPPT) technique achieves 94.6% tracking efficiency without complex data calculation and storage, which are better results compared with those of previous research.
A DVS-Based Burst Mode with Automatic Entrance Point Control Technique in DC-DC Boost Converter for Wearable Devices and IoT Applications
(2017-01-01)
Cheng, Chiao-Hung
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Lin, Li-Chi
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Lin, Jian-He
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Chen, Ke-Horng
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Lin, Ying-Hsi
the proposed dynamic voltage scaling (DVS) based burst mode links the DVS technique in a system on a chip (SoC) and the burst mode operation of the DC-DC converter for further efficiency improving. Conventional burst mode has only one entrance transition point (ETP) between the pulse width modulation (PWM) and the burst mode, so the voltage ripple is high at low DVS voltage while the efficiency is low at high DVS voltage. The proposed DVS-based burst mode uses the automatic entrance point control (AEPC) technique to decide multiple ETP values corresponding to the voltage identification (VID) code from the SoC. The quality enhancement technique deliberately adjusts the burst reference voltage to further reduce the output ripple with acceptable loss of efficiency. The tested DC-DC boost converter with the DVS-based burst mode technique is fabricated in 0.18 mu m CMOS process. Measurement results show that the efficiency is higher than 85% when the output voltage varies from 1.8V to 3.2V (controlled by the DVS) and load current ranges from 0.1mA to 140mA, with peak efficiency 94%.
A High Efficiency and Fast Transient Digital Low-Dropout Assisted Switched-Capacitor Converter for EMI-Free Internet of Everything (IoE) Systems
(2017-01-01)
Chen, Shao-Qi
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Lin, Yen-Ting
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Ma, Yu-Sheng
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Yang, Wen-Hau
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Chen, Ke-Horng
State-of-the-art closed-loop switched-capacitor (SC) designs usually regulate the output voltage by pulse frequency modulation (PFM) with the disadvantage of large electromagnetic interference (EMI). It may cause the failure of the Internet of Everything (IoE) devices. This paper proposes the hybrid digital low drop-out (DLDO) SC converter with a constant switching pulse width modulation (PWM) control for low EMI. Besides, the analog-to-digital current conversion provided by the DLDO due to its fast transient response can predict the desired ratio for the SC and reduce the dip voltage at the same time. The handshaking technique achieves smooth transition in the hybrid architecture. Experimental results show peak efficiency of 85% (closed-loop) and 95% (open loop) since the power converter has fast transient response by the DLDO prediction and reduction of switching power loss. Accurate fine tune operation by the DLDO and smooth handshaking improve load regulation from 49mV to 3mV and undershoot from 263mV to 93mV with a reduced recovery time of 200ns.
A Low Quiescent Current and Cross Regulation Single-Inductor Dual-Output Converter with Stacking MOSFET Driving Technique
(2017-01-01)
Ma, Yu-Sheng
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Yang, Wen-Hau
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Lin, Yen-Ting
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Chen, Hsin
;
Lin, Li-Chi
the stacking MOSFET structure composed of low-voltage devices suffers from deteriorated transient response or large footprint area when capacitor-free or dominant pole compensation low dropout (LDO) regulator biases the driver. Due to self-stabilized feature, the proposed stacking MOSFET driving (SMD) technique effectively drives the power stage and greatly reduces noise interference from the noisy node to achieve low cross regulation (CR) in the single-inductor dual-output (SIDO) converter. Moreover, two inherent low dropout (LDO) regulators in the SMD technique completely regulate two outputs with low quiescent current at no load condition. Experimental results show the tested chip fabricated in 0.25 mu m process with low cross regulation of 0.015mV/mA and ultra-low quiescent current of 5 mu A at no load condition.
High Accuracy Knee Voltage Detection for Primary-Side Control in Flyback Battery Charger
(2017-04-01)
Yang, Shang-Hsien
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Tsai, Tsung-Hsun
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Chen, Hsin
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Chiu, Chao-Chang
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Chen, Ke-Horng
In a primary-side control flyback charger, the accuracy of a conventional knee voltage detection (KVD) approach to obtain the output voltage is influenced by the inclusion of a snubber circuit. Although the snubber circuit dampens the ringing voltages due to switching, it also affect the resonance frequency which would reduce the timing of the sampling circuit, resulting in the inaccurate sampling of output voltage. By analyzing the snubber circuit and its resonance on the primary side, this paper implements a proposed accuracy knee voltage detection (AKVD) technique to compensate for the induced resonance frequency. Furthermore, the proposed constant current (CC) regulator ensures the accuracy of CC mode by compensating the sensing current error caused by the switching delay of the power transistor. A prototype consisting of a test chip fabricated with a 0.5 mu m BCD process demonstrates a voltage accuracy exceeding 99.63%. This is achieved by mitigating abnormal detections and thus ensuring correct control of charging current throughout the charging period.
Implantable Biomedical Device Supplying by a 28nm CMOS Self-Calibration DC-DC Buck Converter with 97% Output Voltage Accuracy
(2015)
Yang, Te-Fu
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Huang, Ru-Yu
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Su, Yi-Ping
;
Balakumar
;
Chen, Ke-Horng
Implantable devices like artificial cardiac pacemakers are generally used to control irregular pulses of heart. For 10-year usage, high accuracy supply voltage is essential with the unavoidable aging of the power system to achieve near-natural beat rhythm. A Self-Calibration DC-DC Buck converter (SC-Buck) is proposed to achieve high output voltage accuracy by eliminating offset caused by mismatch of process, voltage and temperature (PVT). Furthermore, the discontinuity which affects transient performance in conventional offset cancellation is also overcome. Large area occupation, which is required to decrease mismatch in conventional operational amplifier, can be largely decreased according to Monte Carlo analysis. Without trimming process, the proposed SC-Buck technique achieves high accuracy for long-term usage (years) and low cost. The test chip fabricated in UMC 28nm CMOS process proves the output voltage accuracy of 97% since the mismatch of error amplifier can be suppressed from 122% to 1%.
Lossless Inductor Current Control in Envelope Tracking Supply Modulator with Self-Allocation of Energy for Optimzation of Efficiency and EVM
(2016-01-01)
Ynag, Shang-Hsien
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Chen, Ke-Horng
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Wey, Chin-Long
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Lin, Ying-Hsi
;
Lin, Jian-Ru
conventional hybrid supply modulator for envelope tracking (ET) technique requires the linear amplifier to track a RF envelop signal with the help of switching converter to provide average power for high efficiency. Any distortion caused by resistive and inaccurate current sensing will result in increase of power loss and Error Vector Magnitude (EVM). Thus, a lossless inductor current control (LICC) with a closed-loop self allocation technique is proposed to increase efficiency and decrease the EVM. Inductor current ripple information is directly extracted from the gate drive signal of a class-AB linear amplifier and a weighted self-allocation control is applied to optimize for efficiency and EVM. Extra power improvement of 2.5% can be derived. Owing to the removal of a power consuming sensing resistor in conventional design, the efficiency can be effectively improved. The proposed supply modulator is capable of delivering an instantaneous peak power of 3.36W and a bandwidth of 20MHz with an averaged efficiency up to 85%.
Self-adjustable Feed-forward Control and Auto-tracking Off-time Control Techniques for 95% Accuracy and 95% Efficiency AC-DC Non-isolated LED Driver
(2015)
Chen, Hsin
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Chen, Chi-Wei
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Hsieh, Hsueh-Yi
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Chen, Ke-Horng
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Tsai, Tsung-Yen
the non-isolated buck topology for LED driver is proposed to reduce volume and cost without the need of large transformer. Besides, in the entire universal range of AC input voltage, the proposed self-adjusted feed-forward control (SAFFC) technique ensures small variation in the LED current. The auto-tracking off-time control (ATOTC) technique is also adopted to adjust the off time to guarantee the current accuracy is better than that of the peak current control (PCC) technique while and the efficiency is better than that of the hysteresis current control (HCC) technique. Test chip fabricated in VIS 0.5 mu m 700V ultra-high voltage (UHV) process demonstrates power factor higher than 0.97, averaged 95% high accuracy, and 95% high efficiency.
Suppressing Output Overshoot Voltage Technique with 47.1mW/mu s Power-Recycling Rate and 93% Peak Efficiency DC-DC Converter for Multi-core Processors
(2015)
Chien, Meng-Wei
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Yang, Wen-Hau
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Chou, Ying-Wei
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Chen, Hsin-Chieh
;
Chen, Wei-Chung
Conversion efficiency degrades in case of heavy-to-light loading change since state-of-art overshoot reduction techniques simply dissipate redundant energy at the output of buck DC-DC converter. Thus, the proposed dual-mode ripple-recovered compensator (D-RRC) and multi-phase suppressing output overshoot voltage (MP-SOOV) technique uses 33nH bondwire inductance to recycle energy and provides 47.1mW/mu s ultra-fast power-recycling rate to suppress overshoot voltage from 507mV to 95mV with 81.3% improvement when load changes from 1.7A to 0.3A. Experimental results show 93% high efficiency and high-speed operation with only tens of nano second on-time period.
Ultra-Low Voltage Ripple in DC-DC Boost Converter by the Pumping Capacitor and Wire Inductance Technique
(2016-01-01)
Tang, Chen-Fan
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Chen, Ke-Horng
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Wey, Chin-Long
;
Lin, Ying-Hsi
;
Lin, Jian-Ru
overall consideration including bonding wire effects is needed because conventional DC-DC boost converter used in energy harvesting systems suffers from large output voltage ripple in steady state and transient response. Thus, this paper proposed the pumping capacitor and wire inductance (PCWI) technique to suppress output voltage ripple to an ultra-low value. Small steady state voltage across the wire inductance (WI) and continuous WI current can be ensured by an additional pumping capacitor (PC). Moreover, even in case of an ultra-low output voltage ripple, the proposed pseudo-inductor current (PIC) technique regenerates the inductor current information to eliminate the instability problem in conventional ripple-based control techniques. Transient recovery time and output voltage variation can be reduced simultaneously. Test chip was fabricated in 0.18 mu m 5V/24V CMOS process when input voltage of 1.8-5.5V is converted to 12.8V. Experimental results show the ratio of output voltage ripple and output voltage is reduced to 0.04%. Measured power conversion efficiency is around 92% at 100mA and 96% at 0.1mA.
Unsymmetrical Parallel Switched-Capacitor (UP-SC) Regulator with Fast Searching Optimum Ratio Technique
(2017-01-01)
Lin, Yen-Ting
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Yang, Wen-Hau
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Ma, Yu-Sheng
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Lai, Yan-Jiun
;
Chen, Hung-Wei
Different from conventional multiphase switched-capacitor (SC) DC-DC converters, the proposed unsymmetrical parallel switched-capacitor (UP-SC) regulator provides more controllable input variables to increase available conversion ratios for improved load regulation. Even under higher conversion ratio numbers, the UP-SC regulator uses the fast searching optimum ratio (FSOR) technique to search the destined ratio rapidly and to reduce the transient recovery time. Experimental results show the test chip fabricated in 0.25 mu m CMOS process increases the ratio number to 187 and 2389 in 3-stage and 4-stage SC regulators, respectively. Transient recovery time reduces from 26 mu s to 1.5 mu s in case of 7mA load current step.