Browsing by Author "Lin, Jinq-Min"

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New Observation and Analysis of Layout Dependent Effects in Sub-40nm Multi-Ring and Multi-Finger nMOSFETs for High Frequency Applications
(2019-01-01)
Li, Zu-Cheng
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Guo, Jyh-Chyurn
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Lin, Jinq-Min
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交大名義發表
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National Chiao Tung University
Multi-finger (MF) and multi-ring (MR) nMOSFETs were designed and fabricated in 40nm CMOS technology to explore the layout dependent effects in key device parameters and parasitic RC responsible for RF performance. For the first time, the experimental proves the advantages of MR nMOSFETs, such as the increase of effective mobility (mu(eff)), transconductance (g(m)), and channel current (I-DS), and smaller parasitic source resistance (R-S), all of which are in favor of higher speed and higher frequency. However, the undesired increase of 3-D fringing capacitances may bring a critical trade-off influencing high frequency performance. In this paper, new observation and in-depth analysis of the complicated layout dependent effects can facilitate the device layout optimization in the right direction for RF and mm-wave design and applications.
Quasiresonant Control With a Dynamic Frequency Selector and Constant Current Startup Technique for 92% Peak Efficiency and 85% Light-Load Efficiency Flyback Converter
(2014-09-01)
Kang, Yu-Chai
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Chiu, Chao-Chang
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Lin, Moris
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Yeh, Chih-Pu
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Lin, Jinq-Min
The proposed quasiresonant control scheme can be widely used in a dc-dc flyback converter because it can achieve high efficiency with minimized external components. The proposed dynamic frequency selector improves conversion efficiency especially at light loads to meet the requirement of green power since the converter automatically switches to the discontinuous conduction mode for reducing the switching frequency and the switching power loss. Furthermore, low quiescent current can be guaranteed by the constant current startup circuit to further reduce power loss after the startup procedure. The test chip fabricated in VIS 0.5 mu m 500 V UHV process occupies an active silicon area of 3.6 mm(2). The peak efficiency can achieve 92% at load of 80 W and 85% efficiency at light load of 5W.
The Impact of Layout Dependent Intrinsic Parasitic RLC on High Frequency Performance in 3T and 4T Multi-finger nMOSFETs
(2019-01-01)
Guo, Jyh-Chyurn
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Ou, Jyun-Rong
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Lin, Jinq-Min
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
A new observation of significant differences in the high frequency device parameters and performance like f(T) and f(MAX) is identified from the comparison of 3-terminal (3T) and 4-terminal (4T) multi-finger (MF) nMOSFETs. Through an extensive characterization on the intrinsic Z- and Y-parameters, it is found that the major impact comes from the particular increase of intrinsic parasitic resistances and inductances at the source terminal, namely R-s,R-int and L-s,L-int in the 4T MF MOSFETs. The proposed analytical models as a function of key device parameters incorporating the influence of the intrinsic parasitic RLC through high frequencies can accurately predict f(T) and f(MAX) degradation in 4T MF nMOSFETs as well as the complicated layout dependent effects. The experimental results and analytical models can be useful to facilitate MF devices layout optimization for high frequency design and performance improvement.