Browsing by Author "Lin, Jou-Chun"

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A Fast Prototyping Framework for Analog Layout Migration With Planar Preservation
(2015-09-01)
Pan, Po-Cheng
;
Chin, Ching-Yu
;
Chen, Hung-Ming
;
Chen, Tung-Chieh
;
Lee, Chin-Chieh
Analog layout generation in the advanced CMOS design is challenging by its increasing layout constraints and performance requirements. This situation becomes more intricate by the growing parasitic variability and manufacturing reliability. To facilitate the feasibility of template-based layout migration, this paper first introduces a layout preservation, which extracts placement and routing behaviors from an existing layout into a crossing graph via constrained Delaunay triangulation. And later this crossing graph can be migrated into multiple layouts with placement and routing reconnection. The proposed approach also provides a refinement for wire to optimize the performance metrics. This approach is applied to a variable-gain amplifier, a folded-cascode operational amplifier, and a low dropout regulator. The experimental results demonstrate more possibility on layout migration, such that averagely more than 75% routing of migrated layout is generated by our approach. Additionally, it exhibits the productivity with qualified performance on different designs.
Efficient Analog Layout Prototyping by Layout Reuse with Routing Preservation
(2013)
Chin, Ching-Yu
;
Pan, Po-Cheng
;
Chen, Hung-Ming
;
Chen, Tung-Chieh
;
Lin, Jou-Chun
To strive for better circuit performance on analog design, layout generation heavily relies on experienced analog designers' effort. Other than general analog constraints such as symmetry and wire-matching are commonly embraced in many proposed works, analog circuit performance is also sensitive to routing behavior. This paper presents a CDT-based layout extraction to preserve routing behavior of the reference layout. Furthermore, a generalized layout prototyping methodology is proposed based on the layout extraction to achieve routing reuse. The proposed layout prototyping is applied to a variable-gain amplifier and a folded-cascode operational amplifier for both migration and prototypes generation. Experimental results show that our approach effectively reduces design cycle time and simultaneously produces reasonable performance.