Browsing by Author "Lin, KH"

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Analytical spatio-temporal design of Kerr lens mode-locked laser resonators
(1996-08-01)
Lin, KH
;
Hsieh, WF
;
光電工程研究所
;
Institute of EO Enginerring
An analytical method of spatio-temporal design for a Kerr lens mode-locked Ti:sapphire laser is presented. Various spatial and temporal effects are considered to derive simple quadratic equations of the pulse width for both standing- and traveling-wave cavities. By solving the quadratic equation, we obtain the relations between pulse width and other cavity parameters for a given system for optimal design of a Kerr lens mode-locked cavity and to generate the shortest laser pulses. Our theoretical results agree well with the experimental results, and the computation time of this analytic approach for cavity parameters is reduced drastically as compared with an iteratively numerical approach. (C) 1996 Optical Society of America.
Analytical spatio-temporal design of Kerr lens mode-locked laser resonators
(1996-08-01)
Lin, KH
;
Hsieh, WF
;
交大名義發表
;
光電工程學系
;
National Chiao Tung University
An analytical method of spatio-temporal design for a Kerr lens mode-locked Ti:sapphire laser is presented. Various spatial and temporal effects are considered to derive simple quadratic equations of the pulse width for both standing- and traveling-wave cavities. By solving the quadratic equation, we obtain the relations between pulse width and other cavity parameters for a given system for optimal design of a Kerr lens mode-locked cavity and to generate the shortest laser pulses. Our theoretical results agree well with the experimental results, and the computation time of this analytic approach for cavity parameters is reduced drastically as compared with an iteratively numerical approach. (C) 1996 Optical Society of America.
Construction of a wavelength-tunable self-starting Kerr lens mode-locked Ti:sapphire
(1996-04-01)
Lai, JG
;
Lin, KH
;
Juang, DG
;
Hsieh, WF
;
交大名義發表
We have successfully constructed a soft-aperturing, asymmetric cavity Kerr lens mode-locked (KLM) Ti:sapphire laser that is self-starting within 0.5 ms over 780-840 nm wavelength range without any additional starting devices or intracavity hard apertures. We believed that the soft-aperturing mechanism is essential in the self-starting KLM Ti:sapphire lasers and the round trip gain discrimination between CW and KLM modes of the Ti:sapphire laser is sufficient to support self-starting.
Design on ESD protection scheme for IC with power-down-mode operation
(2004-08-01)
Ker, MD
;
Lin, KH
;
電機學院
;
College of Electrical and Computer Engineering
This paper presents a new electrostatic discharge (ESD) protection scheme for IC with power-down-mode operation. Adding a VDD ESD bus line and diodes into the proposed ESD protection scheme can block the leakage current from I/O pin to VDD power line and avoid malfunction during power-down operation. The whole-chip ESD protection design can be achieved by insertion of ESD clamp circuits between VSS power line and both the VDD power line and VDD ESD bus line. Experiment results show that the human-body model (HBM) ESD level of this new scheme can be greater than 7.5 kV in a 0.35-mum silicided CMOS process.
Differential gain and buildup dynamics of self-starting Kerr lens mode-locked Ti:sapphire laser without an internal aperture
(1997-08-01)
Juang, DG
;
Chen, YC
;
Hsu, SH
;
Lin, KH
;
Hsieh, WF
The small-signal differential gain was calculated from the measured average cw and Kerr lens mode-locked (KLM) output powers over the least-misalignment-sensitive region of a completely soft-aperturing, self-starting KLM Ti:sapphire laser. The results indicate that the self-starting condition is reached with this laser operating near the center of the stable range. The simulated location of maximum differential gain and pulse buildup process show good agreement with the experimental results. (C) 1997 Optical Society of America.
Differential gain and buildup dynamics of self-starting Kerr lens mode-locked Ti:sapphire laser without an internal aperture
(1997-08-01)
Juang, DG
;
Chen, YC
;
Hsu, SH
;
Lin, KH
;
Hsieh, WF
The small-signal differential gain was calculated from the measured average cw and Kerr lens mode-locked (KLM) output powers over the least-misalignment-sensitive region of a completely soft-aperturing, self-starting KLM Ti:sapphire laser. The results indicate that the self-starting condition is reached with this laser operating near the center of the stable range. The simulated location of maximum differential gain and pulse buildup process show good agreement with the experimental results. (C) 1997 Optical Society of America.
Double snapback characte'ristics in high-voltage nMOSFETs and the impact to on-chip ESD protection design
(2004-09-01)
Ker, MD
;
Lin, KH
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The double snapback characteristic in the highvoltage nMOSFET under transmission line pulsing stress is found. The physical mechanism of double snapback phenomenon in the high-voltage nMOSFET is investigated by device simulation. With double snapback characteristic in high-voltage nMOSFET, the holding voltage of the high-voltage nMOSFET in snapback breakdown condition has been found to be much smaller than the power supply voltage. Such characteristic will cause the high-voltage CMOS ICs susceptible to the latchup-like danger in the real system applications, especially while the high-voltage nMOSFET is used in the power-rail electrostatic discharge clamp circuit.
Electrostatic discharge protection scheme without leakage current path for CMOS IC operating in power-down-mode condition on a system board
(2006-02-01)
Lin, KH
;
Ker, MD
;
電機學院
;
College of Electrical and Computer Engineering
A new design on the electrostatic discharge (ESD) protection scheme for CMOS IC operating in power-down-mode condition is proposed. By adding a VDD_ESD bus line and diodes, the new proposed ESD protection scheme can block the leakage current from I/O pin to VDD power line to avoid malfunction during power-down-mode operating condition. During normal circuit operating condition, the new proposed ESD protection schemes have no leakage path to interfere with the normal circuit functions. The whole-chip ESD protection design can be achieved by insertion of ESD clamp circuits between VSS power line and both VDD power line and VDD ESD bus line. Experimental results have verified that the human-body-model (HBM) ESD level of this new scheme can be greater than 7.5 kV in a 0.35-mu m silicided CMOS process. Furthermore, output-swing improvement circuit is proposed to achieve the full swing of output voltage level during normal circuit operating condition. (c) 2005 Elsevier Ltd. All rights reserved.
ESD protection design for I/O cells with embedded SCR structure as power-rail ESD clamp device in nanoscale CMOS technology
(2005-11-01)
Ker, MD
;
Lin, KH
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper presents a new electrostatic discharge (ESD) protection design for input/output (I/O) cells with embedded silicon-controlled rectifier (SCR) structure as power-rail ESD clamp device in a 130-nm CMOS process. Two new embedded SCR structures without latchup danger are proposed to be placed between the input (or output) pMOS and nMOS devices of the I/O cells. Furthermore, the turn-on efficiency of embedded SCR can be significantly increased by substrate-triggered technique. Experimental results have verified that the human-body-model (HBM) ESD level of this new proposed I/O cells can be greater than 5 kV in a 130-nm fully salicided CMOS process. By including the efficient power-rail ESD clamp device into each I/O cell, whole-chip ESD protection scheme can be successfully achieved within a small silicon area of the I/O cell.
Low threshold and high power output of a diode-pumped nonlinear mirror mode-locked Nd : GdVO4 laser
(2005-08-22)
Lin, JH
;
Yang, WH
;
Hsieh, WF
;
Lin, KH
;
光電工程學系
We demonstrated nonlinear mirror mode-locking of a diode-pumped Nd:GdVO4 laser by using a 10 mm long KTP crystal. The stable CW mode locking can be reached with the relative low threshold pump power as low as 2.3W. The highest output power of 2.65W at the 10W pump powers are generated with the 121-MHz repetition rate of pulses. It confirms the excellent laser performance of the Nd: GdVO4 for high-peak power of the pulse operation. (c) 2005 Optical Society of America.
MOS-bounded diodes for on-chip ESD protection in a 0.15-mu m shallow-trench-isolation salicided CMOS process
(2003)
Ker, MD
;
Lin, KH
;
Chuang, CH
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Novel diode structures without the shallow trench isolation (STI) across the p/n junction for ESD protection in a 0.15-mum CMOS process are proposed. A NMOS (PMOS) is especially inserted into the diode structure to form the NMOS-bounded (PMOS-bounded) diode, which is used to block the STI isolation across the p/n junction in the diode structure. Without the STI boundary across the p/n junction of diode structure, the proposed PMOS-bounded and NMOS-bounded diodes can provide more effective protection to the internal circuits, as compared to the other diode structures under reverse-biased condition. Such PMOS-bounded and NMOS-bounded dodes are fully process-compatible to general CMOS processes without additional process modification or mask layers.
MOS-bounded diodes for on-chip ESD protection in deep submicron CMOS process
(2005-03-01)
Ker, MD
;
Lin, KH
;
Chuang, CH
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
New diode structures without the field-oxide boundary across the p/n junction for ESD protection are proposed. A NMOS (PMOS) is especially inserted into the diode structure to form the NMOS-bounded (PMOS-bounded) diode, which is used to block the field oxide isolation across the p/n junction in the diode structure. The proposed N(P)MOS-bounded diodes can provide more efficient ESD protection to the internal circuits, as compared to the other diode structures. The N(P)MOS-bounded diodes can be used in the I/O ESD protection circuits, power-rail ESD clamp circuits, and the ESD conduction cells between the separated power lines. From the experimental results, the human-body-model ESD level of ESD protection circuit with the proposed N(P)MOS-bounded diodes is greater than 8 kV in a 0.35-mu m CMOS process.
Multistability in recurrent neural networks
(2006)
Cheng, CY
;
Lin, KH
;
Shih, CW
;
應用數學系
;
Department of Applied Mathematics
Stable stationary solutions correspond to memory capacity in the application of associative memory for neural networks. In this presentation, existence of multiple stable stationary solutions for Hopfield-type neural networks with delay and without delay is investigated. Basins of attraction for these stationary solutions are also estimated. Such a scenario of dynamics is established through formulating parameter conditions based on a geometrical setting. The present theory is demonstrated by two numerical simulations on the Hopfield neural networks with delays.
On-chip ESD protection design with substrate-triggered technique for mixed-voltage I/O circuits in subquarter-micrometer CMOS process
(2004-10-01)
Ker, MD
;
Lin, KH
;
Chuang, CH
;
電機學院
;
College of Electrical and Computer Engineering
A new electrostatic discharge (ESD) protection design, by using the substrate-triggered stacked-nMOS device, is proposed to protect the mixed-voltage I/O circuits of CMOS ICs. The substrate-triggered technique is applied to lower the trigger voltage of the stacked-nMOS device to ensure effective ESD protection for the mixed-voltage I/O circuits. The proposed ESD protection circuit with the substrate-triggered technique is fully compatible to general CMOS process without causing the gate-oxide reliability problem. Without using the thick gate oxide, the new proposed design has been fabricated and verified for 2.5/3.3-V tolerant mixed-voltage I/O circuit in a 0.25-mum salicided CMOS process. The experimental results have confirmed that the human-body-model ESD level of the mixed-voltage I/O buffers can be successfully improved from the original 3.4 to 5.6 kV by using this new proposed ESD protection circuit.
Overview on electrostatic discharge protection designs for mixed-voltage I/O interfaces: Design concept and circuit implementations
(2006-02-01)
Ker, MD
;
Lin, KH
;
電機學院
;
College of Electrical and Computer Engineering
Electrostatic discharge (ESD) protection design for mixed-voltage I/O interfaces has been one of the key challenges of system-on-a-chip (SOC) implementation in nano-scale CMOS processes. The on-chip ESD protection circuit for mixed-voltage I/O interfaces should meet the gate-oxide reliability constraints and prevent the undesired leakage current paths. This paper presents an overview on the design concept and circuit implementations of the ESD protection designs for mixed-voltage I/O interfaces without using the additional thick gate-oxide process. The ESD design constraints in mixed-voltage I/O interfaces, the classification and analysis of ESD protection designs for mixed-voltage I/O interfaces, and the designs of high-voltage-tolerant power-rail ESD clamp circuit are presented and discussed.
The impact of low-holding-voltage issue in high-voltage CMOS technology and the design of latchup-free power-rail ESD clamp circuit for LCD driver ICs
(2005-08-01)
Ker, MD
;
Lin, KH
;
電機學院
;
College of Electrical and Computer Engineering
The holding voltage of the high-voltage devices in snapback breakdown condition has been found to be much smaller than the power supply voltage. Such characteristics will cause the LCD driver ICs to be susceptible to the latchup-like danger in the practical system applications, especially while these devices are used in the power-rail ESD clamp circuit. A new latchup-free design on the power-rail ESD clamp circuit with stacked-field-oxide structure is proposed and successfully verified in a 0.25-mu m 40-V CMOS process to achieve the desired ESD level. The total holding voltage of the stacked-field-oxide structure in snapback breakdown condition can be larger than the power supply voltage. Therefore, latchup or latchup-like issues can be avoided by stacked-field-oxide structures for the IC applications with power supply of 40 V.
Thin-film transistors with polycrystalline silicon films prepared by two-step rapid thermal annealing
(2000-01-15)
Cheng, HC
;
Huang, CY
;
Wang, FS
;
Lin, KH
;
Tarntair, FG
A novel two-step rapid thermal annealing (RTA) process has been developed to significantly reduce the crystallization time for the solid-phase crystallization (SPC) of amorphous silicon films. In comparison with the conventional SPC processes, it not only keeps a low thermal budget but also achieves a larger poly-Si film grain size than that obtained by one-step RTA, and even as large as that obtained by conventional furnace annealing (CFA). Furthermore, poly-Si thin-film transistors fabricated by such a novel annealing scheme possess electrical characteristics superior to those obtained by one-step RTA and comparable to those obtained by long-time CFA.