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Browsing by Author "Lin, Li-Chi"

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    A Digital Reverse Current Self-calibration Technique in 90% High Efficiency Rectified Power Supply for Near Field Communication through Magnetic Field Induction
    (2017-01-01)
    Lin, Li-Chi
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    Chen, Kuan-Yu
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    Yang, Wen-Hau
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    Huang, Ru-Yu
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    Chen, Ke-Horng
    it is crucial in near field communication (NFC) controllers for power source transferred from mutual induction of coils when the devices are battery-off. NFC devices can be operated at the condition of low battery or even battery-off due to the requirement of payment any time. Thus, the proposed wireless power transfer (WPT) power supply can have high efficiency due to the remove of reverse leakage current by the digital reverse current self-calibration (DRCS). NFC standards including A, B, and F can be continuously supplied by the WPT supply system. The WPT power supply with the DRCS technique was fabricated in 0.25 mu m CMOS process can rectify AC source from induction of magnetic field to unregulated DC voltage source and to supply power the NFC controller through low dropout regulator (LDR). Moreover, test chip achieves as high as 92% voltage conversion ratio and 89.4 % power conversion efficiency (PCE) due to reduction of unnecessary current loss.
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    A DVS-Based Burst Mode with Automatic Entrance Point Control Technique in DC-DC Boost Converter for Wearable Devices and IoT Applications
    (2017-01-01)
    Cheng, Chiao-Hung
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    Lin, Li-Chi
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    Lin, Jian-He
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    Chen, Ke-Horng
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    Lin, Ying-Hsi
    the proposed dynamic voltage scaling (DVS) based burst mode links the DVS technique in a system on a chip (SoC) and the burst mode operation of the DC-DC converter for further efficiency improving. Conventional burst mode has only one entrance transition point (ETP) between the pulse width modulation (PWM) and the burst mode, so the voltage ripple is high at low DVS voltage while the efficiency is low at high DVS voltage. The proposed DVS-based burst mode uses the automatic entrance point control (AEPC) technique to decide multiple ETP values corresponding to the voltage identification (VID) code from the SoC. The quality enhancement technique deliberately adjusts the burst reference voltage to further reduce the output ripple with acceptable loss of efficiency. The tested DC-DC boost converter with the DVS-based burst mode technique is fabricated in 0.18 mu m CMOS process. Measurement results show that the efficiency is higher than 85% when the output voltage varies from 1.8V to 3.2V (controlled by the DVS) and load current ranges from 0.1mA to 140mA, with peak efficiency 94%.
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    A Low Quiescent Current and Cross Regulation Single-Inductor Dual-Output Converter with Stacking MOSFET Driving Technique
    (2017-01-01)
    Ma, Yu-Sheng
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    Yang, Wen-Hau
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    Lin, Yen-Ting
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    Chen, Hsin
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    Lin, Li-Chi
    the stacking MOSFET structure composed of low-voltage devices suffers from deteriorated transient response or large footprint area when capacitor-free or dominant pole compensation low dropout (LDO) regulator biases the driver. Due to self-stabilized feature, the proposed stacking MOSFET driving (SMD) technique effectively drives the power stage and greatly reduces noise interference from the noisy node to achieve low cross regulation (CR) in the single-inductor dual-output (SIDO) converter. Moreover, two inherent low dropout (LDO) regulators in the SMD technique completely regulate two outputs with low quiescent current at no load condition. Experimental results show the tested chip fabricated in 0.25 mu m process with low cross regulation of 0.015mV/mA and ultra-low quiescent current of 5 mu A at no load condition.
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    A Single-Inductor Dual-Output Converter With the Stacked MOSFET Driving Technique for Low Quiescent Current and Cross Regulation
    (2019-03-01)
    Chen, Hsin
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    Huang, Chao-Jen
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    Kuo, Chun-Chieh
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    Lin, Li-Chi
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    Ma, Yu-Sheng
    Stacked MOSFET structures made of low-voltage devices suffer from degraded transient response or large footprint when a capacitorless or dominant-pole compensated low-dropout (LDO) regulator biases the driver. Due to the self-stabilizing nature, the proposed stacked MOSFET driver (SMD) technology effectively drives the power stage and greatly reduces the noise at the switching nodes for low cross regulation (CR) in a single-inductor dual-output (SIDO) converter. In addition, two inherent LDO regulators in SMD technology fully regulate the dual outputs with the advantage of low quiescent current at no-load conditions. The experimental results show that the test chip fabricated under the 0.25-mu m process has low CR of 0.015 mV/mA and ultralow quiescent current of 5 mu A under no-load conditions.
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    High-efficiency blue multilayer polymer light-emitting diode fabricated by a general liquid buffer method
    (2008-02-01)
    Tseng, Shin-Rong
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    Meng, Hsin-Fei
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    Yeh, Chi-Hung
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    Lai, Huan-Chung
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    Horng, Sheng-Fu
    A bright, highly efficient blue polymer light-emitting diode is fabricated by spin-coating with multilayer structure. By introducing a liquid buffer layer, the dissolution problem is overcome successfully. This general method can be applied to fabricate arbitrary polymer multilayer structure, in particular the addition of the carrier blocking layers to balance the electron and hole currents and improve the device efficiency. By adding an electron-blocking layer, the external quantum efficiency for blue emission can be increased to 5.5% (9.1 cd/A) which is even higher than the theoretical limit of 5%. The luminance reaches 26,530cd/m(2) and the Commission Internationale de L'Eclairage (CIE) coordinates is (0.15, 0.23). Further more the lifetime is increased by three times relative to the single layer device. (c) 2007 Elsevier B.V. All rights reserved.