Browsing by Author "Lin, Long-Yi"

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A Cost-Effective Stimulus Generator for Battery Channel Characterization in Electric Vehicles
(2014)
Hung, Shao-Feng
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Lin, Long-Yi
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Hong, Hao-Chiao
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電機學院
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College of Electrical and Computer Engineering
The battery management system (BMS) is substantial in diagnosing and controlling the battery modules of emerging electric vehicles (EVs). This paper presents a cost-effective stimulus generator for characterizing the communication channels between the BMS host controller and the battery cells. The characterization data are useful to enhance the reliability of the communication. The proposed stimulus generator only consists of a digital oscillator, a reconfigurable digital Sigma-Delta modulator, and an output driver. The all-digital design saves the power and the hardware cost. The digital oscillator provides digital sine waves with well-controlled frequency and amplitude. The proposed reconfigurable digital Sigma-Delta modulator allows generating pulse-density-modulated (PDM) bit-streams of particular frequencies that cover the whole band of interest. Hence, the test accuracy is no less than that of conventional sinusoidal waves. Simulation results show that the generated stimuli have very high narrow-band SNRs that is essential to test the frequency responses of the channels.
A Study on the Transfer Function Based Analog Fault Model for Linear and Time-Invariant Continuous-Time Analog Circuits
(2016)
Hong, Hao-Chiao
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Lin, Long-Yi
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電機工程學系
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Department of Electrical and Computer Engineering
How to efficiently test analog circuits is an open issue because of the lack of widely-accepted analog fault model. This paper studies the impacts of the parametric faults on the transfer function\'s coefficients of continuous-time and linear-and-time-invariant (LTI) analog circuits from the design\'s point of view. It is found the parametric faults change the coefficients but not the template of the transfer function (TF) of the circuit under test (CUT). Based on this observation, a test procedure that does not need time-consuming fault simulations is proposed. We show the practical TF coefficients of the CUT can be accurately measured by conducting a simple multi-tone test. In addition, conventional coefficient based tests make pass/fail decisions by checking if any coefficient is outside its pre-computed tolerance box. From the design\'s point of view, we propose comparing the frequency responses of the measured TF with the design specification to make the final pass/fail decision, the same as what conventional functional tests do.
Accurate and Fast On-Wafer Test Circuitry for Device Array Characterization in Wafer Acceptance Test
(2019-09-01)
Hong, Hao-Chiao
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Lin, Long-Yi
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電機工程學系
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Department of Electrical and Computer Engineering
This paper proposes an on-wafer test circuitry for rapidly and accurately characterizing the devices under tests (DUTs) of the DUT array in the wafer acceptance test (WAT) to qualify wafers faster and more reliably. The proposed test cell simply comprises a DUT and a selection MOSFET operating in the saturation region as a current buffer when being activated. An analog feedback loop with a replica-biasing circuit tracks the selected DUT's output current and automatically biases the selection MOSFET's gate so as to accurately duplicate the desired setup voltage at the selected DUT's output node. Comparing with conventional designs using the Kelvin sensing scheme to address the switches' IR drops, the proposed design has less transistor counts, shorter test time, and no risk of forward-bias p-n junctions. Consequently, it achieves a lower test cost and a higher test throughput. The whole proposed test circuitry including 1024 NMOS DUTs has been designed and fabricated in 90-nm CMOS. The active area is only 60 mu m by 800 mu m which is small enough to be placed into the scribe line on wafers as conventional WAT circuitry is. Measurement results demonstrate the proposed design's efficiency and capability of revealing local process variations.
An Enhanced Boundary Scan Architecture for Inter-Die Interconnect Leakage Measurement in 2.5D and 3D Packages
(2017-01-01)
Law, Pok Man Preston
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Wu, Cheng-Wen
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Lin, Long-Yi
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Hong, Hao-Chiao
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電機工程學系
3D-IC is a solution to achieve lower cost and higher performance as the transistor density doubles every 18 months following Moore's law. In recent years, Integrated Fan-Out Wafer-Level Chip-Scale Packaging (InFO WLCSP) is one of the most promising packaging technologies for 3D-IC. In InFO WLCSP, there are some inter-die interconnects. We cannot access these interconnects directly. Therefore, it causes 1-2% test coverage loss. As a result, a built-in self-test (BIST) or other design-for-test (DFT) methodology is necessary to test these interconnects. It is easy to detect open defects and short defects leading to large leakage currents with conventional test methods. However, defects leading to small leakage currents are hard to detect, so we focus on these defects in this work. In this paper, we propose a scheme to measure the small leakage current of these inter-die interconnects. The scheme uses IEEE 1149.1 boundary scan interface. Because boundary scan is a well-adopted standard, the scheme can be integrated into any electronic product easily. Beside four mandatory terminals, we add a reference current input. Users can apply current to compare it with the leakage current. For the input EBSC, two OR gates, a MUX, and a current digitizer are added and it is compared with the conventional BSC. A test chip is implemented to verify our design, which uses the one-poly-nine-metal (1P9M) 90nm CMOS technology. Measurement results show that the proposed scheme is able to measure the leakage current of the interconnect. In addition, with the dynamic range of 128nA, the current digitizer has 6-bit resolution.
Design and Experimental Results of a Wireless Power Receiver for the Water Pollution Detection System
(2015)
Chiang, Che-Yi
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Lin, Long-Yi
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Hong, Hao-Chiao
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電機學院
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College of Electrical and Computer Engineering
This paper presents the design and experimental results of a wireless power receiver IC for the water pollution detection system. The system adopts the magnetic resonance method to transmit the wireless power. We adopts the active rectifier with dynamic body biasing scheme to implement the receiver. The receiver IC has been designed and fabricated in 0.35 um CMOS. Measurement results show that when the two coils have diameters of 9.5 cm and 2.2 cm and separated by a distance of 5 cm, the proposed wireless power receiver IC can supply 30.3 mW to a 400 Omega resistive load with a wireless power efficiency of 9.0%.
Design of a 0.20-0.25-V, Sub-nW, Rail-to-Rail, 10-bit SAR ADC for Self-Sustainable IoT Applications
(2019-05-01)
Hong, Hao-Chiao
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Lin, Long-Yi
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Chiu, Yi
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電機工程學系
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Department of Electrical and Computer Engineering
This paper presents a 10-bit SAR ADC operating at a supply voltage (VDD) from 0.200 to 0.250 V. In the proposed ADC structure, the positive input of the comparator is fixed at VDD to bias the comparator's input transistor pair with a sufficient gate-to-source voltage at such a low VDD. We propose an ultra-low VDD temperature-compensated bias generator to bias the comparator for addressing the severe temperature-dependent issue of the MOSFETs in the comparator, which operate in the deep subthreshold region. Detailed circuit analysis and derivation of design requirements are presented. A double-boosted and low-leakage sampling switch is also proposed to alleviate the severe leakage issue at low sampling rates. A test chip has been designed and fabricated in 180-nm CMOS. The ADC core occupies only 0.024 mm(2). Measurement results show that the ADC achieves stable performance in the VDD range. At 0.225 V, the DNL and INL are within +1.04/-0.66 and +0.97/-1.04 LSB in the rail-to-rail input range, respectively. The measured peak SNDR at the Nyquist input frequency is 49.2 dB at 450 S/s. The whole ADC totally consumes 0.85 nW at 0.225 V including circuit leakages. The sub-nW power consumption makes it well suited for self-sustainable Internet-of-Things applications.
Design of a Fault-Injectable Fleischer-Laker Switched-Capacitor Biquad for verifying the Static Linear Behavior Fault Model
(2013)
Lin, Long-Yi
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Hong, Hao-Chiao
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電機資訊學士班
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Undergraduate Honors Program of Electrical Engineering and Computer Science
This paper presents the design of a fully-differential low-pass SC biquad filter that allows injecting the parametric and catastrophic faults to it. The design is for the verification of the static linear behavior (SLB) fault model which covers multiple parametric and catastrophic analog faults of sampled-data systems. The SLB fault model assumes that a circuit under test (CUT) has a fixed z-domain transfer function (TF) template and the faults alter nothing but the coefficients of the TF. To verify this basic assumption, we first retrieve all coefficients of the TF of the fault-injected biquad from the test results of a three-tone test following the diagnosis-after-test (DAT) procedure. Then, we conduct simulations with other stimulus tones and check if the tested responses fit in those predicted by the retrieved TF. Experimental results verify that the fixed TF template assumption holds for all the faults that we injected.
Testing the Fleischer-Laker Switched-Capacitor Biquad Using the Diagnosis-After-Test Procedure
(2012)
Hung, Shao-Feng
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Lin, Long-Yi
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Hong, Hao-Chiao
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電機工程學系
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Department of Electrical and Computer Engineering
This paper demonstrates an efficient diagnosis-after-test (DAT) procedure for testing the Fleischer-Laker SC biquad based on the static linear behavior (SLB) analog fault model. For typical switched-capacitor (SC) filter design, the transfer functions are mainly determined by capacitor ratios. Therefore, the practical capacitor ratios are important parameters for designers to diagnose their designs. The DAT procedure can not only test for the real transfer function of the SC biquad for making reliable pass/fail decision without conducting many tests, but also diagnose the capacitor ratios of the SC biquad. With the diagnosis results, designers can find out which capacitors cause the failure and revise the design for a better yield. Mathematical analysis shows that the entire DAT procedure requires only a three-tone test, which implies a very short test time. A second-order low-pass filter adopting the E-circuit of the Fleischer-Laker SC biquad is taken as a test example. Simulation results show the DAT procedure can provide good test accuracy with the three-tone test data. In addition, the test achieves a 100% parametric fault coverage of the capacitor ratios defined by the SLB fault model for the Fleischer-Laker SC biquad.