Browsing by Author "Lin, Louis Y-Z"

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Coupling-Aware Functional Timing Analysis for Tighter Bounds: How Much Margin Can We Relax?
(2017-01-01)
Lin, Jack S-Y
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Lin, Louis Y-Z
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Huang, Ryan H-M
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Wen, Charles H-P
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電機工程學系
As the manufacturing technology keeps scaling, crosstalk noise induces a greater impact on timing. Although many previous works proposed techniques like timing correlation, functional correlation and path refinement to consider crosstalk noise during static timing analysis, they often suffered from descendant problems including overly-pessimistic timing bound, bad aggressor selection and false paths. Therefore, in this paper, a coupling-aware functional timing analysis tool named CA-FTA is proposed to tame the three problems stated above and to derive a tighter timing bound for the true longest path. Experimental results show that CA-FTA averagely reduces timing bounds of those obtained from crosstalk STA (with path refinement) by 7.26% on several ISCAS'85 and ISPD-2012 benchmark circuits (in particular, by 34.6% for b19). As a result, CA-ETA successfully solves the aggressor-selection problem as well as the false-path problem and relaxes more margins when considering crosstalk noise.
P4-TPG: Accelerating Deterministic Parallel Test Pattern Generation by Preemptive, Proactive, and Preventive Schedulings
(2019-01-01)
Lin, Louis Y-Z
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Hsu, Charles Chia-Hao
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Wen, Charles H-P
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電機工程學系
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Department of Electrical and Computer Engineering
According to the prior research, a deterministic parallel test pattern generation (TPG) engine was realized and generated the same test pattern set the serial automatic test pattern generation does during acceleration. However, for retaining the determinism, tremendous idle time is observed when different tasks (either dependent or independent) were synchronized among threads. Therefore, a new deterministic parallel TPG engine called P4-TPG is developed and incorporates preemptive, proactive, and preventive schedulings to further save/reuse the idle time during acceleration. In P4-TPG, preemptive scheduling first modifies the thread flow and brings forward, as many latter tasks as possible, to the idle time. Next, proactive scheduling inserts prospective TPG tasks of unprocessed faults to the remaining idle time and increases the overall utilization of threads. Last, preventive scheduling dynamically skips faults incompatible with the working pattern per thread and shortens the fault list during fault compaction. The experimental results show that P4-TPG not only generates the same test pattern set as the serial TPG does but also achieves averagely 10.36x speedups, is 96.6% better than the prior research, using 12 threads on 18 benchmark circuits.
Unleashing Parallelism With Minimal Test Inflation in Multi-Threaded Test Pattern Generation
(2018-01-01)
Lin, Louis Y-Z
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Wen, Charles H-P
;
電機工程學系
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Department of Electrical and Computer Engineering
Shared-memory systems enable parallel computing for the automatic test pattern generation (ATPG). Although the existing techniques for parallel ATPG reach near-linear speedup, test inflation becomes a common problem in its practicality. Therefore, this paper proposes a multi-threaded test pattern generation called MT-TPG that can suppress test inflation and accelerate fault processing, simultaneously, to retain high parallelism. For suppressing test inflation, hard-fault shuffling (HFS) and concurrent-fault interruption (CFI) are involved to avoid repeated detection of the same fault among different threads. For accelerating fault processing, the potentially-droppable-fault removal (PDFR) and single-pattern parallelfault simulation (SPPFSim) collectively drop not-yet-detected faults as early as possible for shortening the overall execution time of ATPG. According to our experimental results, the HFS and CFI can successfully suppress test inflation to < 4% on 17 benchmark circuits; PDFR and SPPFSim can achieve 13.7X speedup using 16 threads on average. As a result, MT-TPG is proven effective at unleashing parallelism with minimal test inflation on shared-memory systems.