Browsing by Author "Lin, M"

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A multilevel interconnect technology with intrametal air gap for high-performance 0.25-mu m-and-beyond devices manufacturing
(1999-11-01)
Lin, M
;
Chang, CY
;
Huang, TY
;
Lin, ML
;
電子工程學系及電子研究所
A multilevel interconnect technology with an intra metal air gap has been developed to reduce the interconnect delay time for versatile. and quick turnaround-time foundry manufacturing. The air-gap method has been successfully applied to 0.25 mu m IC technology and shown to be effective in reducing the parasitic interconnect capacitance. Measurements of various ring oscillators confirm that the smallest delay time is indeed achieved with the air-gap method, compared with other methods using either conventional high-density-plasma (HDP) oxide or low-dielectric-constant spin-on-glass (SOG) as the gap-filling insulating materials. Moreover, the oscillator delay time is found to depend critically on not only the size of the air gap, but also the position of the air gap. Best results in terms of delay time reduction are obtained when the air-gap is positioned in the middle between the two metal lines, and extends both above and below the metal lines to effectively reduce the fringing capacitance. We have also measured the leakage current between adjacent metal lines and confirmed that our new metal intel connect structure with an air gap does not exhibit any appreciable leakage and appears to be suitable For high-performance foundry applications. Lastly, the polarization and thermal characteristics of the air-gap structure were compared with conventional gap-filling methods.
Leakage current reduction of chemical-vapor-deposited Ta2O5 films on rugged polycrystalline silicon electrode for dynamic random access memory application
(1999-04-01)
Lin, M
;
Chang, CY
;
Huang, TY
;
Shieh, WY
;
電子工程學系及電子研究所
In this paper we describe the electrical and physical characterizations of Ta2O5 films on rapid thermal nitrided (RTN) rugged polycrystalline silicon electrodes for 256 M dynamic random access memory (DRAM) application. To overcome the higher leakage on Ta2O5 films with rugged poly-Si bottom electrodes, we have successfully employed a light oxidation on rugged poly-Si grains for improving the acute angle of surface morphology, and a post-treatment with rapid thermal nitridation of N2O on Ta2O5 films to reduce the leakage. In addition, a RTN pre-treatment is also applied to prevent rugged poly-Si oxidation during a Ta2O5 film deposition that compromises the effective Ta2O5 thickness. Our results show that Ta2O5 film with an effective thickness of 1.4 nm (physical thickness=10 nm) and a low leakage current density of less than 1 X 10(-8) A/cm(2), suitable for 256 M DRAM application, can be achieved. Our results also show that while a light oxidation on rugged poly-Si grains could improve the acute angle between the rugged poly-Si and its congruent amorphous silicon sub-layer, over oxidation on rugged poly-Si grains could degrade the leakage current and the time dependent dielectric breakdown (TDDB) characteristics of the stacked capacitor.
Rugged surface polycrystalline silicon film formed by rapid thermal chemical vapor deposition for dynamic random access memory stacked capacitor application
(1998-06-01)
Lin, M
;
Chang, CY
;
Huang, TY
;
Kuo, UJ
;
電子工程學系及電子研究所
Polycrystalline silicon films with a rugged surface (rugged poly-Si), deposited by a single-wafer rapid thermal chemical vapor deposition (RTCVD) system suitable for 12 inch wafer fabrication, are studied and the films have been successfully applied to bottom storage electrodes for stacked capacitors in dynamic random access memory cells. Our data show that the rugged poly-Si is actually formed by the nucleation generation on the amorphous silicon surface and subsequent crystalline growth during the annealing step following deposition. We also determined that a wide temperature window exists for the formation of rugged poly-Si (i.e., +/- 15 degrees C) using RTCVD, which is wider than that using low pressure chemical vapor deposition (LPCVD) (i.e., +/-3 degrees C) and ultra high vacuum chemical vapor deposition (UHVCVD) (i.e., +/-10 degrees C). Stacked capacitors fabricated using rugged poly-Si and thin silicon oxide/silicon nitride dielectric film show that for a rugged poly-Si storage electrode with a 60 nm top-layer and 645 degrees C annealing, an effective surface area of approximately 2.9 times that of a conventional poly-Si film electrode is obtained.