Browsing by Author "Lin, M. H."

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A New Observation of Strain-Induced Slow Traps in Advanced CMOS Technology with Process-Induced Strain Using Random Telegraph Noise Measurement
(2009)
Lin, M. H.
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Hsieh, E. R.
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Chung, Steve S.
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Tsai, C. H.
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Liu, P. W.
In this paper, the hot-carrier induced oxide trap and its correlation with enhanced degradation in strained CMOS devices have been reported for the first time. First, the I(D)-RTN (Drain Current Random Telegraph Noise) has been employed to study the HC stress induced slow oxide traps in strained nMOSFETs and pMOSFETs. Secondly, different behavior of the slow traps in nMOSFET and pMOSFET has been observed. Results show that the vertical compressive strain generates extra oxide defects and induces more scattering after the HC stress in CESL nMOSFET. This vertical strain in CESL, also contributes to a non-negligible amount of extra device degradation. While, SiGe S/D pMOSFET shows different behavior in that the compressive strain in this structure shows no impact on its reliability.
Effects of length scaling on electromigration in dual-damascene copper interconnects
(2008-04-01)
Lin, M. H.
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Lin, M. T.
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Wang, Tahui
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
The electromigration short-length effect in dual-damascene Cu interconnects has been investigated through experiments on lines of various lengths (L), being stressed at a variety of current densities (j), and using a technologically realistic three-level structure. This investigation represents a complete study of the short-length effect after a well-developed dual-damascene Cu process. Lifetime measurement and resistance degradation as a function of time were used to describe this phenomenon. It has been found that the sigma of log-normal distribution increased as the current density-length product decreased. The statistical distribution of the critical volume fits the sigma curve well. Lower jL(2) values show large sigma values because of back-stress-induced TTF (time-to-fail) dispersion. A simplified equation is proposed to analyze the experimental data from various combinations of current density and line length at a certain temperature. The resulting threshold-length product (jL)(C) value appears to be temperature dependent, decreasing with an increase in temperature in a range of 250-300 degrees C. (c) 2007 Elsevier Ltd. All rights reserved.
Effects of width scaling and layout variation on dual damascene copper interconnect electromigration
(2007-12-01)
Lin, M. H.
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Chang, K. P.
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Su, K. C.
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Wang, Tahui
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電子工程學系及電子研究所
Electromigration versus line width in the 0.12-10 mu m range and the configuration of the via/line contact in dual damascene Cu has been investigated. There are two scenarios for width scaling impact on electromigration. One is the width < 1 mu m region, in which the MTF shows a weak width dependence, except for the via-limited condition. The other is the width > 1 mu m region, in which the MTF shows a strong width dependence. A theory was proposed to explain the observed behavior. For polycrystalline lines (width > 1 mu m), the dominant diffusion paths are a mixture of grain boundary and surface diffusion. The activation energy for the dominant grain boundary transport (width > 1 mu m) is approximately 0.2 eV higher than that of the dominant surface transport (width similar to 1 mu m). The derived activation energies for grain-boundary and surface diffusion are obtained from Cu drift velocity under electromigration stressing. The mechanisms governing the electromigration lifetime of interconnects leads to via interconnect design rules for maximizing lifetime being identified. (C) 2006 Elsevier Ltd. All rights reserved.
Effects of width scaling, length scaling, and layout variation on electromigrationin in dual damascene copper interconnects
(2006)
Lin, M. H.
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Chang, K. P.
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Su, K. C.
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Wang, Tahui
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電子工程學系及電子研究所
Investigation of Electrical Characteristics on 25-nm InGaAs Channel FinFET Using InAlAs Back Barrier and Al2O3 Gate Dielectric
(2017-01-01)
Lin, M. H.
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Lin, Y. C.
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Lin, Y. S.
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Sun, W. J.
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Chen, S. H.
We investigated an N-type III-V FinFET with a 25-nm In0.53Ga0.47As channel and a 300-nm In0.52Al0.48As barrier layer on an InP substrate. The In0.52Al0.48As barrier layer is used to suppress leakage current from the InP substrate and the 10-nm Al2O3 film deposited by atomic layer deposition (ALD) can be a robust gate dielectric to mitigate interface traps. The on to off current ratio is approximately three orders of magnitude, the subthreshold swing (SS) is 350 mV/dec, and the maximum driving current density is 130 mu A/mu m at V-G = 1.5 V for InGaAs FinFET with a fin width of 40 nm and gate length of 200 nm. (c) 2017 The Electrochemical Society. All rights reserved.
Metal-Gate/High-kappa/Ge nMOS at Small CET With Higher Mobility Than SiO2/Si at Wide Range Carrier Densities
(2013-02-01)
Liao, C. C.
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Ku, T. C.
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Lin, M. H.
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Zeng, Lang
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Kang, Jinfeng
High-performance TaN/TiLaO/La2O3/SiO2/(111)-Ge nMOSFETs show high mobility of 432 cm(2)/V . s at 10(13) cm(-2) carrier density (N-s), good 1.05 junction ideality factor, and small subthreshold swing of 101 mV/dec, at a small 1.1-nm capacitance-equivalent thickness (CET). This is the first report of higher mobility in the Ge nMOSFET than SiO2/Si universal mobility at wide medium-high N-s range and small CET of 1.1 nm, which is attributed to using the (111)-Ge substrate, 30-ns laser annealing, SiO2 interfacial layer, and YbGex/n-Ge contact.
On the Electrical Characteristics of Ferroelectric FinFET Using Hafnium Zirconium Oxide with Optimized Gate Stack
(2018-10-27)
Lin, M. H.
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Fan, C. C.
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Hsu, H. H.
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Liu, C.
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Chen, K. M.
We investigated a short-channel ferroelectric FinFET using a ferroelectric HfZrO thin film as gate dielectrics, and scaled down the channel length to 60 nm to study the short-channel effect and the ferroelectricity. The HfZrO FinFETs exhibited improved short-channel performance including subthreshold swing improvement and reduced drain-induced barrier lowering effect. By using pulsed I-V measurement method, we confirmed that the thickness tradeoff between HfZrO ferroelectric layer and buffered layer are critical to alleviate the influence of interface traps and simultaneously obtain the ferroelectricity in HfZrO FinFET devices with the consideration of sidewall traps. Interface traps may cause unwanted off-state leakage current and mismatching negative capacitance. Here, we demonstrated that the ferroelectric behavior can be achieved by simultaneously increasing HfZrO thickness to obtain the optimized polarization and adopt appropriate buffered layer to screen the traps effect under ferroelectric domain switching. (C) 2018 The Electrochemical Society.
The Understanding of Strain-Induced Device Degradation in Advanced MOSFETs with Process-Induced Strain Technology of 65nm Node and Beyond
(2010)
Lin, M. H.
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Hsieh, E. R.
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Chung, Steve S.
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Tsai, C. H.
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Liu, P. W.
In this paper, the origin of the strained-induced degradation in the MOSFETs with process-induced strain has been investigated by the ID-RTN ( Drain Current Random Telegraph Noise) technique. The process-induced strain on devices will make worse the device reliability, as reported in [1-2]. First, the ID-RTN has been employed to study the reliability of two different types of strain devices, i.e., the CESL strain and SiC S/D strain on nMOSFETs. Both CESL and SiC S/D nMOSFETs exhibit poorer reliability compared to bulk devices. However, their impacts to the much worse degradation are different. Results demonstrated that, for the strain in CESL device, it introduced extra mobility scattering in the vertical direction, while in SiC S/D device, the tensile strain along the channel causes an increase of trap generation via the horizontal field only. The CESL process introduces an additional compressive strain vertical to the channel such that it shows much worse reliability than the SiC S/D ones.