Browsing by Author "Lin, MJ"

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Characterizing trench-gate power metal-oxide-semiconductor field effect transistor with multi-layer dielectrics at the trench bottom
(2003-11-01)
Lin, MJ
;
Liaw, CW
;
Chang, FL
;
Cheng, HC
;
電子工程學系及電子研究所
Power devices with a high switching speed and a low conduction resistance are crucially important in power conversion circuits. In this study, a trench-gate power metal-oxide-semiconductor field effect transistor (MOSFET) with a high-density cell design 20.6 Mcell/cm(2) was implemented for the first time using multilayer dielectrics with an oxide-nitride-oxide (ONO) structure at the bottom of the trench. The thick ONO dielectric layers at the bottom of the trench compensate for the increase in Miller capacitance per unit area as the cell density increases. The resulting device exhibits excellent characteristics of gate charge, switching power loss, gate oxide quality and practical process stability, superior to those of the conventional structure. An n-channel 25.8 V trench gate MOSFET with a specific on-resistance of 0.15 mOmegam(2), and R-ON x Q(GD) figure-of-merit 41 mOmega.nC is presented.
Fabrication of trench-gate power MOSFETs by using a dual doped body region
(2004-07-01)
Juang, MH
;
Chen, WT
;
Ou-Yang, CI
;
Jang, SL
;
Lin, MJ
Fabrication of trench-gate power MOSFETs by using a dual doped body region has been proposed to further improve the device performance. For the usual scheme that employs a uniform doped body region, a device with a blocking voltage larger than 30 V and a specific on-state resistance of about 1.0 Omegacm can be obtained via the proper choice of trench depth, epitaxial thickness, and body doping concentration. On the other hand, a dual doped body region is produced by dual high-energy and low-energy implantation of boron dopant. By this scheme, a device with a blocking voltage larger than 30 V and a specific on-state resistance of about 0. 8 Omegacm can be further achieved. Hence, with reducing the cell pitch size to be below 2 mum, this device fabrication scheme should be promising and practical for achieving a specific on-resistance smaller than 0. 1 mOmegacm2 and a blocking voltage higher than 30 V. (C) 2004 Elsevier Ltd. All rights reserved.
Fast integration of low orbiter's trajectory perturbed by the earth's non-sphericity
(1998-10-01)
Hwang, C
;
Lin, MJ
;
土木工程學系
;
Department of Civil Engineering
A fast algorithm is proposed to integrate the trajectory of a low obiter perturbed by the earth's nonsphericity. The algorithm uses a separation degree to define the low-degree and the high-degree acceleration components, the former computed rigorously, and the latter interpolated from gridded accelerations. An FFT method is used to grid the accelerations. An optimal grid type for the algorithm depends on the trajectory's permissible error, speed, and memory capacity. Using the non-spherical accelerations computed from EGM96 to harmonic degree 360, orbit integrations were performed for a low orbiter at an altitude of 170 km. For a separation degree of 50, the new algorithm, together with the predict-pseudo correct method, speeds up the integration by 145 times compared to the conventional algorithm while keeping the errors in position and velocity below 10(-4) m and 10(-7) mis for a 3-day arc.
Fast integration of low orbiter's trajectory perturbed by the earth's non-sphericity
(1998-10-01)
Hwang, C
;
Lin, MJ
;
土木工程學系
;
Department of Civil Engineering
A fast algorithm is proposed to integrate the trajectory of a low obiter perturbed by the earth's nonsphericity. The algorithm uses a separation degree to define the low-degree and the high-degree acceleration components, the former computed rigorously, and the latter interpolated from gridded accelerations. An FFT method is used to grid the accelerations. An optimal grid type for the algorithm depends on the trajectory's permissible error, speed, and memory capacity. Using the non-spherical accelerations computed from EGM96 to harmonic degree 360, orbit integrations were performed for a low orbiter at an altitude of 170 km. For a separation degree of 50, the new algorithm, together with the predict-pseudo correct method, speeds up the integration by 145 times compared to the conventional algorithm while keeping the errors in position and velocity below 10(-4) m and 10(-7) mis for a 3-day arc.
Investigation of a 450 V rating silicon-on-insulator lateral-double-diffused-metal-oxide-semiconductor fabrication by 12/25/5/40 V bipolar-complementary metal-oxide-semiconductor double-diffused metal-oxide-semiconductor process on bulk silicon substrate
(2004-07-01)
Chang, FL
;
Lin, MJ
;
Liaw, CW
;
Liao, TC
;
Cheng, HC
In this study, traditional bipolar-complementary metal oxide semiconductor (CMOS)-double diffused metal oxide semiconductor (DMOS) (BCD) technology, which is designed for only lateral bipolar (Bipolar, 12V BVCEO and 25V BVCBO), complementary metal oxide semiconductor (CMOS, 1.2V threshold voltage) and double diffused metal oxide semiconductor (DMOS, 40 V breakdown voltage) transistors on the bulk silicon wafer, has been successfully utilized directly in silicon on insulator lateral double diffused metal oxide semiconductor (SOI LDMOS) for the first time without changing any trial parameters. To simultaneously display the characteristics of high-power, high-speed and high-frequency, the results of output characteristics, switch and microwave performance must be moderate instead of optimum. In addition, according to the experimental results, it is proved that Bulk-BCD technology simultaneously enables high-speed, high-frequency and high-blocking-voltage applications-such as those in high-voltage integrated circuit switches (ns-range) and RF power amplifiers (MHz range to GHz range)-using a SOI wafer.
Investigation of the gate dielectric oxidation treatment in trench gate power devices
(2001)
Lin, MJ
;
Liaw, CE
;
Chang, JJ
;
Chang, FL
;
Hsu, CCH
In respect of trench gate power devices, it is difficult to achieve satisfactory gate oxide leakage current, breakdown voltage and reliability characteristics. Trench etching process induced silicon surface damage, convex corner and contamination, which will degrade the silicon dioxide quality. It is convinced that post etching treatment including sacrificial oxidation and chemical dry ashing can improve the gate oxide quality significantly. In this article, we study the treatment of a trench capacitor with sacrificial oxidation and classify the effect of each parameter in the oxidation process. The benefit of N2O annealing after gate oxidation will also be discussed. The evaluations of I-V and CV characteristics are the main considerations of the gate oxide quality in this research.
Lateral superjunction reduced surface field structure for the optimization of breakdown and conduction characteristics, in a high-voltage lateral double diffused metal oxide field effect transistor
(2003-12-01)
Lin, MJ
;
Lee, TH
;
Chang, FL
;
Liaw, CW
;
Cheng, HC
Superjunction devices are reported to provide better high-voltage operation characteristics than conventional abrupt junction devices in silicon power applications. In this study, the superjunction reduced surface field (SJ-RESURF) lateral double diffused metal oxide semiconductor field effect transistor (LDMOSFET) is fabricated on a bulk silicon wafer to improve the operating characteristics of high-voltage devices. By introducing the p-type strips in the drift region, higher doping concentration of the drift region can be adopted to reduce the conduction resistance. The SJ-RESURF LDMOSFET with a specific on-resistance of 3.53 Omega(.)mm(2), a breakdown voltage of 335 V and a drift length of 30 mum, is demonstrated; its turn on-resistance is 25% better than that of the conventional structure. The turn-on resistance, breakdown behavior, device geometry, temperature, and charge balance mechanics of the SJ-RESURF LDMOSFET are examined herein.
Modeling and design of the high performance step SOI-LIGBT power devices by partition mid-point method
(2003-10-01)
Chang, FL
;
Lin, MJ
;
Lee, GY
;
Chen, YS
;
Liaw, CW
In this paper, a partition method is proposed to Study the high voltage devices with the step doping profile for the first time. It has been proposed that its breakdown voltage can be approached to that of the linearly graded devices with similar forward voltage drop (V-cc). In addition, by this method, the breakdown voltage can be deduced and its corresponding issue location is also fingered out in the step drift region. Furthermore. in order to reduce the undesirable additional masks, the degraded factor (D) is developed to obtain better performance with the least number of frames. Eventually, a 660 V step analytical results are compared with a 606.6 V MEDICI Simulation and this shows that the partition method is very effective. (C) 2003 Elsevier Ltd. All rights reserved.
Novel low-temperature polycrystalline-silicon power devices with very-low on-resistance using excimer laser-crystallization
(2004)
Cheng, HC
;
Chang, FL
;
Lin, MJ
;
Tsai, CC
;
Liaw, CW
Low-temperature poly-Si lateral double-diffused metal oxide semiconductor (LTPS LDMOS) with high voltage and very low on-resistance has been achieved using excimer laser crystallization at 400 degreesC substrate heating for the first time. The ON/OFF current ratios were 2.96 x 10(5) and 6.72 x 10(6) while operating at V-ds = 0.1 and 10 V, respectively. The maximum current limit was up to 10 mA and maximum power limit could be enhanced over 1 W at V-ds = 90 V and V-gs = 20 V. The R-on,R-sp with dimensions of W/L-ch = 600 mum/12 mum could be significantly decreased 6.67 x 10(2) times in magnitude as compared with conventional offset drain thin-film-transistors. (C) 2004 The Electrochemical Society.