Browsing by Author "Lin, Mark Po-Hung"

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A Novel Analog Physical Synthesis Methodology Integrating Existent Design Expertise
(2015-02-01)
Wu, Po-Hsun
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Lin, Mark Po-Hung
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Chen, Tung-Chieh
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Yeh, Ching-Feng
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Li, Xin
Analog layout design has been a manual, time-consuming, and error-prone task for decades. To speed up layout design time for a new design, analog layout designers prefer referring to legacy designs and layouts rather than starting from scratch, or thoroughly applying placement and routing tools because legacy layouts contain pretty much design expertise. Motivated by such layout design process, this paper presents the first knowledge-based physical synthesis methodology to generate new layouts by integrating existent design expertise. The proposed approach can automatically analyze legacy design data including circuits, layouts, and constraints, extract matched sub-circuits between new and legacy designs, and generate multiple layouts for the new design by utilizing the quality-approved legacy layouts as much as possible. Experimental results show that the proposed methodology can achieve high layout reusage rate, and hence the designers\' layout preference can be successfully reserved.
Analog Layout Synthesis with Knowledge Mining
(2015)
Wu, Po-Hsun
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Lin, Mark Po-Hung
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Ho, Tsung-Yi
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資訊工程學系
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Department of Computer Science
To reduce layout design time, analog layout designers prefer referring to legacy designs and layouts rather than starting from scratch, or thoroughly applying placement and routing tools because legacy layouts contain pretty much design expertise. Therefore, this paper presents the first knowledge-based layout synthesis methodology to generate new layouts by integrating existent design expertise contained in the quality-approved legacy layouts as much as possible. Experimental results show that the proposed methodology with knowledge mining can achieve high layout reusage rate and hence the designers\' layout preference can be successfully reserved.
Corner-Stitching-Based Multilayer Obstacle-Avoiding Component-to-Component Rectilinear Minimum Spanning Tree Construction
(2020-03-01)
Su, Yen-Yu
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Wang, Shuo-Hui
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Wu, Wei-Liang
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Lin, Mark Po-Hung
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電子工程學系及電子研究所
Engineering change orders (ECOs) are pervasively applied to modern physical design of nanometer integrated circuits for cost-effective design changes. After applying ECO, a net may become open, which results in a large number of disconnected net components. Each net component further consists of a set of connected net shapes and vias on different layers. It is very challenging to efficiently and effectively identify all disconnected net components and find an obstacle-avoiding minimal-cost routing path among those net components. This paper introduces an open-net finder and an open-net connector based on the corner-stitching data structure for open-net routing, and proposes a new method of constructing a multilayer obstacle-avoiding component-to-component rectilinear minimum spanning tree. The preliminary idea and implementation of the proposed method had received the first place award in ICCAD-2017 CAD contest. This paper further details the complete idea of the proposed method. Experimental results show that the proposed open-net finder and connector outperform the top three open-net routers in the ICCAD-2017 CAD contest and two latest published works, with better routing costs and much shorter runtime.