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Browsing by Author "Lin, Shian-Ru"

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    A 4.2 nW and 18 ppm/degrees C Temperature Coefficient Leakage-Based Square Root Compensation (LSRC) CMOS Voltage Reference
    (2019-05-01)
    Huang, Chao-Jen
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    Lai, Yan-Jiun
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    Yang, Yu-Jheng Ou
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    Chen, Hung-Wei
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    Kuo, Chun-Chieh
    State-of-the-art CMOS-based voltage reference suffer from a trade-off between power dissipation and temperature coefficient (TC) due to the limited order of compensation in an advanced process which features a low supplied voltage (1 similar to 1.2 V). The proposed voltage reference with leakage-based square root compensation (LSRC) technique bias the substrate to offset TC with ultra-low leakage current (100 similar to 300 pA). On the other hand, the architecture provides an extensible order of compensation which is independent of voltage headroom. The two LSRC branches voltage reference implemented in 40 nm CMOS process achieves a within-wafer sigma/mu of 0.204 and a TC of 18 ppm/degrees C with a power consumption of 4.2 nW.
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    A 97% Maximum Efficiency Fully Automated Control Turbo Boost Topology for Battery Chargers
    (2019-11-01)
    Muniandi, Balakumar
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    Huang, Chao-Jen
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    Kuo, Chun-Chieh
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    Yang, Te-Fu
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    Chen, Ke-Horng
    In this paper, the proposed topology of a fully automated control (FAC) battery charger that provides turbo-boost operation and fully automated detection without any feedback from the system is discussed. It uses closed-loop control for automatic system load detection and automatically adjusts the battery discharge current. The advantages include shortened battery discharge time and maximum power provided by the adapter. Therefore, the FAC technique is flexible for any load system that is limited to battery chargers with the turbo boost mode support. In addition, to avoid over discharge, a battery protection circuitry is also included. The test chip is fabricated using a 0.25- $\mu \text{m}$ CMOS process, with a maximum efficiency of 94.58 & x0025; when the charger operates in the turbo boost mode, and achieves 97 & x0025; maximum efficiency when the charger operates in buck charge mode.
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    A Buck Power Factor Correction Converter with Predictive Quadratic Sinusoidal Current Modulation and Line Voltage Reconstruction
    (2016-09)
    Yang, Shang-Hsien
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    Meng, Che-Hao
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    Chiu, Chao-Chang
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    Chang, Chih-Wei
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    Chen, Ke-Horng
    A buck power factor correction (PFC) converter operating in continuous conduction mode (CCM) is influenced by the dead zone, which introduces distortion related to the input line voltage. Such phenomenon limits the maximum power factor (PF) and the minimum total harmonic distortion (THD) achievable. By deriving a methodology to achieve predictive line voltage reconstruction (PLVR), the influence of the dead zone is mitigated. With the prediction of quadratic sinusoidal current modulation ((PSCM)-C-2), the line current is shaped into sinusoid waveform that is in-phase with input line voltage, crucial for. Consequently, the proposed CCM buck PFC can achieve high PF, low THD, and efficiency simultaneously. A test chip was fabricated in 0.5-mu m Bipolar-CMOS-DMOS (BCD) process. The experimental results show a peak PF of 0.95 and a peak efficiency of 98% at 110 Vac.
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    A CMOS Switched-Capacitor Boost Mode Envelope Tracking Regulator with 4% Efficiency Improvement at 7.7dB PAPR for 20MHz LTE Envelope Tracking RF Power Amplifiers
    (2019-01-01)
    Kumari, Neha
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    Yang, Shang-Hsien
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    Chen, Ke-Horng
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    Lin, Ying-Hsi
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    Lin, Shian-Ru
    In this paper, the switched -capacitor boost (SCB) mode envelope tracking (ET) technique with a switched-capacitor circuit and a low dropout (LDO) regulator are used to replace conventional envelope tracking regulators. At a Peak-to-Average Power Ratio (PAPR) of 7.7dB common for LTE communication, the efficiency is 72%, which is 4% higher than the theoretical limit of conventional ET techniques. When PAPR increases from 6.1dB to 7.3dB, the conventional ET efficiency decreases from 82% to 69% whereas the SCB mode increases by 2%.
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    A Constant-on-Time Control DC-DC Buck Converter With the Pseudowave Tracking Technique for Regulation Accuracy and Load Transient Enhancement
    (2018-07-01)
    Yang, Wen-Hau
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    Huang, Chao-Jen
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    Huang, Han-Hsiang
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    Lin, Wei-Ting
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    Chen, Ke-Horng
    Constant-on-time (COT) control with an additional current feedback path in conventional buck converters can remove the need of large equivalent series resistance (ESR) at the output capacitor but it induces degraded output voltage regulation accuracy and slow transient response owing to opposite reaction between the output voltage and the additional current feedback information. Therefore, this paper proposes the pseudowave tracking (PWT) technique to reduce the load-dependent dc offset voltage of output load regulation while keeping the fast transient response similar to conventional COT buck converter with large ESR. The PWT technique further improves the transient response instantly by extending on-time and off-time periods during light-to-heavy and heavy-to-light load changes, respectively. The test chip fabricated in 28 nm CMOS process has demonstrated the improvement of offset voltage from 42 to 4 mV, while the transient response can be improved to 4 and 5 mu s with load changes from 0.3 to 1.7 A and vice versa, respectively.
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    A Digital Reverse Current Self-calibration Technique in 90% High Efficiency Rectified Power Supply for Near Field Communication through Magnetic Field Induction
    (2017-01-01)
    Lin, Li-Chi
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    Chen, Kuan-Yu
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    Yang, Wen-Hau
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    Huang, Ru-Yu
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    Chen, Ke-Horng
    it is crucial in near field communication (NFC) controllers for power source transferred from mutual induction of coils when the devices are battery-off. NFC devices can be operated at the condition of low battery or even battery-off due to the requirement of payment any time. Thus, the proposed wireless power transfer (WPT) power supply can have high efficiency due to the remove of reverse leakage current by the digital reverse current self-calibration (DRCS). NFC standards including A, B, and F can be continuously supplied by the WPT supply system. The WPT power supply with the DRCS technique was fabricated in 0.25 mu m CMOS process can rectify AC source from induction of magnetic field to unregulated DC voltage source and to supply power the NFC controller through low dropout regulator (LDR). Moreover, test chip achieves as high as 92% voltage conversion ratio and 89.4 % power conversion efficiency (PCE) due to reduction of unnecessary current loss.
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    A Dynamic Bootstrap Voltage Technique for a High-Efficiency Buck Converter in a Universal Serial Bus Power Delivery Device
    (2016-04-01)
    Chen, Wei-Chung
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    Chou, Ying-Wei
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    Chien, Meng-Wei
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    Chen, Hsin-Chieh
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    Yang, Shang-Hsien
    The dynamic bootstrap voltage (DBV) technique is proposed to keep high efficiency over wide ranges of load currents for high-power universal serial bus devices. The silicon area of the embedded power management with the DBV technique in the system-on-a-chip can be effectively reduced to 50% of the conventional design with a P-type high-side power MOSFET. Test chips fabricated in 0.25-mu m CMOS process showed a 92% peak efficiency from 1 mA to 1 A. The maximum driving current was higher than 5 A, and the efficiencywas 88%. Compared with the efficiency of the converter without the DBV technique, the efficiency of the converter with DBV technique was improved by about 28%.
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    A Fully Integrated Asymmetrical Shunt Switched-Capacitor DC-DC Converter With Fast Optimum Ratio Searching Scheme for Load Transient Enhancement
    (2019-09-01)
    Lin, Yen-Ting
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    Lai, Yan-Jiun
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    Chen, Hung-Wei
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    Yang, Wen-Hau
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    Ma, Yu-Sheng
    This paper presents a modified negator-based switched-capacitor (NSC) dc-dc converter to achieve fine-grained voltage conversion ratios. Based on a concept of reconfiguring several 2: 1 switched-capacitor (SC) converters in series and parallel at the last stage, the proposed asymmetrical shunt SC (ASSC) converter provides more controllable variables of forward gain and feedback gain to decide different power path interconnections and increase the available conversion ratios, with a little sacrifice of its slow switching limit output impedance. The switching loss of the bottom-plate parasitic capacitance in the ASSC converter is less than the switching loss of the NSC topology because the two moderate voltages instead of the power rail are fed to the last stage 2: 1 SC unit and reduce the voltage swing. The bottom-plate swapping prototype further reduces the parasitic loss at high conversion ratios. To handle a large number of conversion ratios in closed-loop regulation, the ASSC converter uses the fast optimum ratio searching (FORS) technique, which evaluates the transient voltage drop to quickly search for target ratios and reduce the transient recovery time. A three-stage ASSC converter achieving 187 conversion ratios is fully integrated in the test chip, which is fabricated in 0.25-mu m CMOS process with an active area of 7.14 mm(2). Furthermore, 2389 conversion ratios can be derived in theory for a four-stage ASSC converter. The proposed reconfigurable SC converter provides an output voltage range of 0.4 to 2.8 V under no load conditions, and greater than 80% power efficiency at an output voltage level of 0.9 to 1.5 V over a load range of 3 to 9.5 mA. Due to the FORS technique, the measured transient recovery time is reduced from 7 to 1.5 mu s in case of load current step of 7 mA.
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    A High Current efficiency Stacked Digital Low Dropout Array with True-Random-Noise Injection and Ultralow Output Ripple for Power-Side Channel Attack Protection
    (2019-01-01)
    Lee, Cheng-Yen
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    Huang, Tzu-Ping
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    Chen, Ke-Horng
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    Lin, Ying-Hsi
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    Lin, Shian-Ru
    This paper proposes a stacked digital low dropout (DLDO) array with three stacked groups to improve security and efficiency, consuming 1/3 of the input current in the prior art. The security is improved by two mechanisms. The advanced encryption standard (AES) engine can be one of point of loads (POLs) hidden in the deeper levels to minimize the disturbance from the AES to the input current. The other is the digital balanced interleave control (DBIC) receives random sources from internal leakage current frequency generator (LCFG) to generate randomly noise current to further hide the current interference caused by the AFS. Due to DBIC anti LCFG techniques, the correlation between input current and AES current is low to 0.006, which is 150 times lower than that of conventional DLDO.
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    A High Efficiency and Fast Transient Digital Low-Dropout Regulator With the Burst Mode Corresponding to the Power-Saving Modes of DC-DC Switching Converters
    (2020-04-01)
    Lin, Jian-He
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    Yang, Shang-Hsien
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    Muniandi, Balakumar
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    Ma, Yu-Sheng
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    Huang, Chia-Ming
    The proposed digital low-dropout regulator uses nonlinear switching control (NLSC) technique to suppress voltage ripple to less than 6mV when the switching noise voltage of a switching regulator operating in a power-saving mode is greater than 50mV. In addition, the NLSC technique improves the current efficiency by reducing the quiescent current to less than 10 A and reduces the switching power loss through variable switching frequency control. With a load step of 1-20mA, the transient response time is 1.3 s and the peak current efficiency is 99.8 at heavy loads.
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    A Low-THD Class-D Audio Amplifier With Dual-Level Dual-Phase Carrier Pulsewidth Modulation
    (2015-11-01)
    Yang, Shang-Hsien
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    Yang, Yuan-Han
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    Chen, Ke-Horng
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    Lin, Ying-Hsi
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    Tsai, Tsung-Yen
    In this paper, a class-D audio amplifier which combines the advantages of the phase-shifted carrier pulse-width modulation (PWM) and the multiple-level carrier PWM is proposed with a dual-level dual-phase carrier (DLDPC) PWM. The proposed closed-loop amplifier includes a second-order integrator and a DLDPC triangular wave generator. Two sets of 180. out-of-phase triangular waves are used as carriers, and each set has its respective offset voltage level with nonoverlapping amplitude. By performing the double Fourier analysis, it can be found that the linearity can be enhanced and the distortion can be reduced with the proposed modulation. Experimental results show that the proposed fully differential DLDPC PWM class-D audio amplifier features a total harmonic distortion lower than 0.01% with an output voltage swing of +/- 5 V.
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    A Pseudo-Ramp Controlled Three Level Buck Converter with an Auto-ripple Cancellation Technique for Low Output Voltage Ripple in Sub-threshold Applications
    (2018-01-01)
    Chu, Li-Cheng
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    Chen, Shao-Qi
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    Chen, Ke-Horng
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    Lin, Ying-Hsi
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    Lin, Shian-Ru
    In high switching frequency and low duty conversion, the on-time in duty cycle is restrained to brief period. The three-level converter extends the on-time to two times larger. By Pseudo-Ramp Controller (PRC) and Auto-Ripple Cancellation (ARC) Topology, flying capacitors are balanced to 50% input voltage with the accuracy of duty cycle improves 11 times and 3mV output voltage ripple.
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    A Single-Inductor Dual-Output Converter With the Stacked MOSFET Driving Technique for Low Quiescent Current and Cross Regulation
    (2019-03-01)
    Chen, Hsin
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    Huang, Chao-Jen
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    Kuo, Chun-Chieh
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    Lin, Li-Chi
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    Ma, Yu-Sheng
    Stacked MOSFET structures made of low-voltage devices suffer from degraded transient response or large footprint when a capacitorless or dominant-pole compensated low-dropout (LDO) regulator biases the driver. Due to the self-stabilizing nature, the proposed stacked MOSFET driver (SMD) technology effectively drives the power stage and greatly reduces the noise at the switching nodes for low cross regulation (CR) in a single-inductor dual-output (SIDO) converter. In addition, two inherent LDO regulators in SMD technology fully regulate the dual outputs with the advantage of low quiescent current at no-load conditions. The experimental results show that the test chip fabricated under the 0.25-mu m process has low CR of 0.015 mV/mA and ultralow quiescent current of 5 mu A under no-load conditions.
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    A Single-Inductor Triple-Output Converter with an Automatic Detection of DC or AC Energy Harvesting Source for Supplying 93% Efficiency and 0.05mV/mA Cross Regulation to Wearable Electronics
    (2019-01-01)
    Nagateja, T.
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    Chen, Shao-Qi
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    Chu, Li-Cheng
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    Chen, Ke-Horng
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    Lin, Ying-Hsi
    the proposed single-inductor triple-output (SITO) converter can accept both DC battery voltage and AC energy harvesting voltage to provide a triple step up and down outputs. Storing the energy to the H-bridge capacitor first and pumping it later can ensure a continuous inductor current for reducing the output voltage ripple by 67%. Due to the H-bridge, the inductor current value is reduced to 1/5X to achieve high efficiency of 93% under the current loading of 120mA. Moreover, the proposed PWM and the adaptive on-time hybrid controller uses different modulation methods in a single controller to meet the requirements of different multiple outputs.
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    A Temperature Compensated 61-W Class-E Soft-Switching GaN-Based Active Diode Rectifier for Wireless Power Transfer Applications
    (2019-01-01)
    Yang, Shang-Hsien
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    Chen, Ke-Horng
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    Lin, Ying-Hsi
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    Lin, Shian-Ru
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    Tsai, Tsung-Yen
    The proposed 6.78-MHz Class-E receiver features a soft-switching and temperature-compensated GaN-based active diode (GAD) rectifier design. Using the temperature dependence of the relationship between the driving voltage and the on-resistance of the switch, the gate-source control voltage of GaN can be adjusted to mitigate efficiency variations based on temperature effects. Moreover, a phase shift comparator activation controller is based on the direct relationship between the phase delay on the gate drive signals and the output power. The temperature dependency voltage offset of the comparator is alleviated with auto-zeroing. GAD rectifier ensures energy transfer up to 61 W and 6.8 A, high efficiency of 92%, and low harmonic distortion of 2.1%.
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    A Three-Level Single-Inductor Triple-Output Converter with an Adjustable Flying-Capacitor Technique for Low Output Ripple and Fast Transient Response
    (2017-01-01)
    Chu, Li-Cheng
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    Yang, Wen-Hau
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    Zhang, Xiao-Qing
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    Lai, Yan-Jiun
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    Chen, Ke-Horng