Browsing by Author "Lin, Shih-Chin"

Now showing 1 - 7 of 7

Alternate Hammering Test for Application-Specific DRAMs and an Industrial Case Study
(2012)
Huang, Rei-Fu
;
Yang, Hao-Yu
;
Chao, Mango C. -T.
;
Lin, Shih-Chin
;
電子工程學系及電子研究所
This paper presents a novel memory test algorithm, named alternate hammering test, to detect the pairwise word-line hammering faults for application-specific DRAMs. Unlike previous hammering tests, which require excessively long test time, the alternate hammering test is designed scalable to industrial DRAM arrays by considering the array layout for potential fault sites and the highest DRAM-access frequency in real system applications. The effectiveness and efficiency of the proposed alternate hammering test are validated through the test application to an eDRAM macro embedded in a storage-application SoC.
Effects of microwave heating on dielectric and piezoelectric properties of PZT ceramic tapes
(2008-04-01)
Chen, Yun-Tien
;
Sheu, Ching-Iuan
;
Lin, Shih-Chin
;
Cheng, Syh-Yuh
;
交大名義發表
Commercial lead zirconate titanate (PZT) perovskite powders were used to fabricate ceramic tape and then sintered by microwave and conventional methods. Both dielectric and piezoelectric properties of PZT ceramic tapes were studied in terms of sintering process. X-ray diffraction analysis (XRD) and scanning electron microscopy (SEM) show the PZT perovskite phase with smaller grain size and dense microstructure can be obtained at a lower sintering temperature by microwave process. It was also observed that shrinkage ratio and bulk density of the tapes sintered at 800 degrees C were obtained about 19% and 7.46 g/cm(3) by the microwave heating method, respectively, that is corresponding to those values of sintered PZT tapes at 950 degrees C by conventional process. Moreover, the dielectric constant and maximum permittivity are increased about 30% as compared with conventional processing method. The experimental results demonstrated that the characteristics of the PZT tapes could be significantly improved by microwave heating method. These results demonstrate that such a simple approach can upswing the piezoelectric and dielectric properties of these tapes by using microwave process with a short heating time. (C) 2007 Elsevier Ltd and Techna Group S.r.l. All rights reserved.
Electrochemical fabrication and magnetic properties of highly ordered silver-nickel core-shell nanowires
(2008-01-31)
Lin, Shih-Chin
;
Chen, San-Yuan
;
Chen, Yun-Tien
;
Cheng, Syh-Yuh
;
交大名義發表
Ordered silver-nickel core-shell nanowire arrays were successfully fabricated by electrodeposition. The ordered silver nanowire arrays embedded in a porous alumina template were first fabricated from an aqueous solution of Ag(NO3)(2) and Ac(NH3). After removing out the template, the obtained silver nanowire arrays were subsequently electrodeposited with nickel at 1.6-2.6 V and 60 degrees C using the electrolyte composed of NiSO4, NiCl2 and H3BO3. Transmission electron microscopy observation revealed that a similar to 15 nm thick nickel film was coated on the surface of the silver nanowires with about 200 nm in diameter. It was found that the silver nanowires with nickel coating showed enhanced magnetic properties in comparison to that of pure silver nanowires. The magnetic force microscope image of silver-nickel core-shell nanowires showed magnetic domain state. In addition, the hysteresis loops of the silver-nickel nanowire arrays showed a coercive field of 180 Oe, almost independent of the applied magnetic field. However, it was observed that a larger magnetic domain was found in parallel direction than that in perpendicular direction. (c) 2007 Elsevier B.V. All rights reserved.
Fault Models for Embedded-DRAM Macros
(2009)
Chao, Mango C. -T.
;
Yang, Hao-Yu
;
Huang, Rei-Fu
;
Lin, Shih-Chin
;
Chin, Ching-Yu
In this paper, we compare embedded-DRAM (eDRAM) testing to both SRAM testing and commodity-DRAM testing, since an eDRAM macro uses DRAM cells with an SRAM interface. We first start from an standard SRAM test algorithm and discuss the faults which are not covered in the SRAM testing but should be considered in the DRAM testing. Then we study the behavior of those faults and the tests which can detect them. Also, we discuss how likely each modeled fault may occur on eDRAMs and commodity DRAMs, respectively.
Improved Current Density with Al(2)O(3) Coated ZnO Nanorod in Hybrid Solar Cell
(2010-07-01)
Lin, Shih-Chin
;
Chen, San-Yuan
;
Peng, Cheng-Hsiung
;
材料科學與工程學系
;
Department of Materials Science and Engineering
Heterojunction photovoltaic devices consisting of hybrid p-type organic Cu-phthalocyanine and inorganic n-type Al(2)O(3) nanoparticle-coated aligned ZnO nanorods were fabricated. With microwave treatment, an interaction occurred between the Al(2)O(3) and ZnO, as evidenced from TEM image. This interaction shifts the absorption peak of the aligned nanorods from the UV region to visible light and subsequently causes more charge generation. For 5 mol% Al(2)O(3) nanoparticle-coated aligned ZnO nanorods treated with microwaves of 600 W for 300 sec, the maximum incident photon to electron conversion and energy conversion efficiencies under simulated sunlight of AM1.5G (10 mW/cm(2)) are 0.036 mA and 1.32%, respectively.
Improved Current Density with Al2O3 Coated ZnO Nanorod in Hybrid Solar Cell
(2010-07-01)
Lin, Shih-Chin
;
Chen, San-Yuan
;
Peng, Cheng-Hsiung
;
材料科學與工程學系
;
Department of Materials Science and Engineering
Heterojunction photovoltaic devices consisting of hybrid p-type organic Cu-phthalocyanine and inorganic n-type Al2O3 nanoparticle-coated aligned ZnO nanorods were fabricated. With microwave treatment, an interaction occurred between the Al2O3 and ZnO, as evidenced from TEM image. This interaction shifts the absorption peak of the aligned nanorods from the UV region to visible light and subsequently causes more charge generation. For 5 mol% Al2O3 nanoparticle-coated aligned ZnO nanorods treated with microwaves of 600 W for 300 sec, the maximum incident photon to electron conversion and energy conversion efficiencies under simulated sunlight of AM1.5G (10 mW/cm(2)) are 0.036 mA and 1.32%, respectively.
Testing Methodology of Embedded DRAMs
(2012-09-01)
Yang, Hao-Yu
;
Chang, Chi-Min
;
Chao, Mango C. -T.
;
Huang, Rei-Fu
;
Lin, Shih-Chin
"The embedded-DRAM(eDRAM) testing mixes up the techniques used for DRAM testing and SRAM testing since an eDRAM core combines DRAM cells with an SRAM interface (the so-called 1T-SRAM architecture). In this paper, we first present our test algorithm for eDRAM testing. A theoretical analysis to the leakage mechanisms of a switch transistor is also provided, based on that we can test the eDRAM at a higher temperature to reduce the total test time and maintain the same retention-fault coverage. Finally, we propose a mathematical model to estimate the defect level caused by wear-out defects under the use of error-correction-code circuitry, which is a special function used in eDRAMs compared to commodity DRAMs. The experimental results are collected based on 1-lot wafers with an 16 Mb eDRAM core."