Browsing by Author "Lin, Shun-Hua"

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Block-Level Thermal Model for Floorplan Stage in VLSI Design Flow
(2008)
Lin, Shun-Hua
;
Yan, Jin-Tai
;
Chiueh, Herming
;
電信工程研究所
;
Institute of Communications Engineering
Thermal issues have become a determinant factor to result in very large scale integrated (VGSI) circuits work or malfunction. For this reason, the paper proposed an efficient block-level thermal model for temperature calculation in the floorplan stage among the integrated circuit (IC) design flow. Furthermore, the model accurately profiles the temperature difference between all thermal blocks and overcomes the very long computational time issue existing in traditional tile-based thermal model. We not only prove the timing complexity by theory but also use five floorplan benchmarks to test our model. Observing the experimental results, the temperature calculation times for all benchmarks are really direct ratio of total amount of blocks. Hence our block-level thermal model really can reduce the temperature calculating time and provide useful temperature differences for rearranging the floorplan.
Logical Effort Model Extension with Temperature and Voltage Variations
(2008)
Wu, Chun-Hui
;
Lin, Shun-Hua
;
Chiueh, Herming
;
電信工程研究所
;
Institute of Communications Engineering
The method of "Logical Effort Delay Model" allows designers to quickly estimate delay time and optimize logic paths. But the previous variances of logical effort models do not mention how to handle process, voltage, and temperature (PVT) variations appropriately, which may induce a serious misestimate. According to simulation results, delay time increases 21% while temperature increasing from 0 C to 125 C, and increases 2X while supply voltage decreasing from IV to 0.5V in 90nm process. Thus a simple linear extended logical effort g, I/g=(m(t)t+b(t))V(DD)+C, supporting for temperature t and supply voltage V(DD) variations is presented. The proposed model enables designers to estimate the logic path delay and to optimize an N-stage logic network under different temperature and supply voltage conditions. After validation, the accuracy of this new extended logical effort model can achieve about 90%.