Browsing by Author "Lin, T. W."

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Chip-Level Characterization and RTN-Induced Error Mitigation beyond 20nm Floating Gate Flash Memory
(2018-01-01)
Lin, T. W.
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Ku, S. H.
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Cheng, C. H.
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Lee, C. W.
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Ijen-Huang
Vt instability caused by random telegraph noise (RTN) in floating gate flash memories beyond 20nm is studied comprehensively. Experiments reveal that the RTN would cause Vt distribution with a kinked tail which re-distributes to a "Gaussian-like" shape rapidly and was measured by the self established Budget Product Tester (BPT). A Multi-Times Verify (MTV) algorithm to mitigate the statistical tail, thus enlarging operation window is also exhibited by BPT. In further, a probability model to portray the compact Vt distribution under MTV is proposed. Finally, the impact of MTV on lowering the requirement of Error-correcting code (ECC) bit is also demonstrated.
Error Characterization and ECC Usage Relaxation beyond 20nm Floating Gate NAND Flash Memory
(2018-01-01)
Ku, S. H.
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Lin, T. W.
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Cheng, C. H.
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Lee, C. W.
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Chen, Ti-Wen
Endurance of floating gate flash memories at 19nm node and beyond is studied comprehensively. Experiments reveal that the random telegraph noise (RTN) would degrade the read margin with a tail, which quickly reshapes into a symmetric Gaussian form in a lightly-stressed state. After heavy stress, the lower part of tail would spread further while the upper part keeps roughly overlapped with that during fresh. This unique behavior, which was firstly measured by the self-established Budget Product Tester (BPT), can be explained by stress-induced hole trap creation. To investigate the impact of RTN on operation window, a novel algorithm of Multi-Times-Verify accompanied with the optimal Read-Retry (MTVR2) is proposed and validated by BPT. The advantage of MTVR2 to reduce the requirement of Error-Correcting Code (ECC) bit is demonstrated. Finally, the improvement of bit error rate (BER) in TLC operation with MTVR(2 )is also evaluated.
Optimization of gate insulator material for GaN MIS-HEMT
(2016)
Lin, Y. C.
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Lin, T. W.
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Wu, C. H.
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Yao, J. N.
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Hsu, H. T.
Metal-insulator-semiconductor (M-I-S) structure has been employed for GaN HEMTs to suppress gate leakage current. In this work, various gate insulator materials including SiO2, HfO2, La2O3, HfO2/SiO2 and La2O3/SiO2 were investigated for GaN MIS-HEMT application. It is found that GaN MIS-HEMT with La2O3/SiO2 composite oxide results in better device performance and reliability as compared to other gate insulator materials.