Browsing by Author "Lin, TA"

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A low-power H.264/AVC decoder
(2005)
Lin, TA
;
Liu, TM
;
Lee, CY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this paper, we can save memory access in inter and intra prediction by adopting the proposed memory-efficient decoding ordering. In our proposed hierarchical syntax parser, gated clock technique can be effectively applied to reduce power. Simulation shows the proposed design consumes 88mW in real time decoding 1080HD video sequence.
A memory-efficient deblocking filter for H.264/AVC video coding
(2005)
Liu, TM
;
Lee, WP
;
Lin, TA
;
Lee, CY
;
電子工程學系及電子研究所
A memory-efficient architecture design for de-blocking filter in H.264/AVC is presented. We use the novel data arrangement of Column-of-Pixel to facilitate the memory access and reuse the pixel value. Further, we propose a hybrid filter scheduling to improve the system throughput. As compared with some existing approaches of realizing de-blocking filter [1] [2], the proposed design saves about one-half of processing cycles. With novel data arrangement and hybrid filter scheduling, an efficient architecture design is implemented. Further, it is evaluated on H.264 system and easily achieved real-time decoding with 1080 HD (1920x1088@30fps) when working frequency is 100MHz.
A new motion compensation design for H.264/AVC decoder
(2005)
Wang, SZ
;
Lin, TA
;
Liu, NM
;
Lee, CY
;
電子工程學系及電子研究所
Motion compensation is always the main bottleneck in real-time or high quality video applications; thus, fast and efficient motion compensation is necessary. In this paper, a new motion compensation design is presented to overcome large calculation time of complicated motion vector prediction. (MVP) algorithm and high motion resolution in H.264/AVC. By applying 4x4 block based parallelism and context switch buffers in our design, it can efficiently reduce memory access and increase data reuse probability such that achieve real-time decoding with 1080HD (1920x1088) at 100 MHz and search range [-64,+63.75].
An H.264/AVC decoder with 4x4-block level pipeline
(2005)
Lin, TA
;
Wang, SZ
;
Liu, TM
;
Lee, CY
;
電子工程學系及電子研究所
In this paper, we propose a 4x4-block level pipelining architecture with instantaneous switching scheme and optimal decoding ordering of H.264/AVC decoder. Compared with conventional H.264/AVC video decoders [1)[2], which adopt macroblock level pipelines, our proposed 4x4-block level pipelining architecture of H.264/AVC decoder achieves better hardware utilization. Moreover, our proposed decoding ordering can effectively save memory access and reduce processing cycles, which results in 260,000 MB/s under 100MHZ clock frequency. By adopting these two techniques, our proposed design supports real time decoding with 1080HD (1920x1088) video sequence in 30fps (244,800 MB/s required) and level 4 of baseline profile.
Predictive equalizer design for DVB-T system
(2005)
Lin, TA
;
Lee, CY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this paper, we propose several new channel predictive equalizers designed for ETSI DVB-T systems. In conventional DVB-T equalizer designs, the storage of 3 symbols is needed in order to do interpolation of CFR in time axis. This huge amount of storage can be eliminated in our proposed predictive equalizers. We present 3 kinds of predictive equalizers to predict the trend of channel frequency response and Doppler Effect. After simulation and comparison among these 3 kinds of predictive equalizers and conventional 2-D linear interpolated equalizer, we can choose the 1(st) order predictive equalizer with the acceptable performance for the low cost solution on equalizer design for DVB-T system.