Browsing by Author "Lin, TJ"

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A compact DSP core with static floating-point arithmetic
(2006-02-01)
Lin, TJ
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Lin, HY
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Chao, CM
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Liu, CW
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Jen, CW
A multimedia system-on-a-chip (SoC) usually contains one or more programmable digital signal processors (DSP) to accelerate data-intensive computations. But most of these DSP cores are designed originally for standalone applications, and they must have some overlapped (and redundant) components with the host microprocessor. This paper presents a compact DSP for multi-core systems, which is fully programmable and has been optimized to execute a set of signal processing kernels very efficiently. The DSP core was designed concurrently with its automatic software generator based on high-level synthesis. Moreover, it performs lightweight arithmetic-the static floating-point (SFP), which approximates the quality of floating-point (FP) operations with the hardware similar to that of the integer arithmetic. In our simulations, the compact DSP and its auto-generated software can achieve 3X performance (estimated in cycles) of those DSP cores in the dual-core baseband processors with similar computing resources. Besides, the 16-bit SFP has above 40 dB signal to round-off noise ratio over the IEEE single-precision FP, and it even outperforms the hand-optimized programs based on the 32-bit integer arithmetic. The 24-bit SFP has above 64 dB quality, of which the maximum precision is identical to that of the single-precision FP. Finally, the DSP core has been implemented and fabricated in the UMC 0.18 mu m 1P6M CMOS technology. It can operate at 314.5 MHz while consuming 52mW average power. The core size is only 1.5 mmx1.5 mm including the 16 KB on-chip memory and the AMBA AHB interface.
A novel register organization for VLIW digital signal processors
(2005)
Lin, TJ
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Lee, CC
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Liu, CW
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Jen, CW
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電子工程學系及電子研究所
This paper presents a novel register organization for VLIW DSPs. The simulation results show the performance of a DSP with the proposed register file is comparable with state-of-the-art DSPs. However, the proposed register file can save 89.7% area of a conventional centralized one, while reducing its access time by 68.6%.
An efficient VLIW DSP architecture for baseband processing
(2003)
Lin, TJ
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Chang, CC
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Lee, CC
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Jen, CW
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電子工程學系及電子研究所
The VLIW processors with static instruction scheduling and thus deterministic execution times are very suitable for high-performance real-time DSP applications. But the two major weaknesses in VLIW processors prevent the integration of more functional units (FU) for a higher instruction issuing rate - the dramatically growing complexity in the register file (RF), and the poor code density. In this paper, we propose a novel ring-structure RF, which partitions the centralized RF into 2N sub-blocks with an explicit N-by-N switch network for N FU. Each sub-block only requires access ports for a single FU We also propose the hierarchical VLIW encoding with variable-length RISC-like instructions and NOP removal. The ring-structure RF saves 91.88% silicon area and reduces 77.35% access time of the centralized RF. Our simulation. results show that the proposed instruction set architecture with the exposed ring-structure RF has comparable performance with the state-of-the-art DSP processors. Moreover, the hierarchical VLIW encoding can save 32%similar to50% code sizes.
Area-effective FIR filter design for multiplier-less implementation
(2003)
Lin, TJ
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Yang, TH
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Jen, CW
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
The hardware complexity of digital filters is not controllable by straightforwardly rounding the coefficients to the quantization levels. In this paper, we propose an effective alternative that distributes a pre-defined addition budget to the multiplier-less FIR filters, which takes into account the common sub-expression sharing inside the computations. We successfully integrate a heuristic common sub-expression elimination (CSE) algorithm and the coefficient quantization by successive approximation proposed by Li et al. Besides, we also propose an improved search algorithm for an optimal scale factor to settle the coefficients collectively into the quantization space. Simulation results show that CSE effectively reduces 29.1%similar to31.5% budgets for comparable filter responses. Besides, the improved scale factor exploration helps to find an identical or a better (never worse) quantization result with only 32.67%similar to44.53% run time, whether or not CSE is applied.
Cascade-configurable and scalable DSP environment
(2002)
Lin, TJ
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Jen, CW
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
As the complexity of embedded systems grows rapidly, it is common to accelerate critical tasks with hardware. Designers usually use off-the-shelf components or licensed IP cores to shorten the time to market, but the hardware/software interfacing is tedious, error-prone and usually not portable. Besides, the existing hardware seldom matches the requirements perfectly. CASCADE, the proposed design environment as an alternative, generates coprocessing datapaths from the executing algorithms specified in C/C++ and attaches these datapaths to the embedded processor with an auto-generated software driver. The number of datapaths and their internal parallel functional units are scaled to fit the application. It seamlessly integrates the design tools of the embedded processor to reduce the re-training/design efforts and maintains short product development time as the pure software approaches. A JPEG encoder is built in CASCADE successfully with an auto-generated four-MAC accelerator to achieve 623% performance boost for our video application.
Coefficient optimization for area-effective multiplier-less FIR filters
(2003)
Lin, TJ
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Yang, TH
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Jen, CW
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
This paper presents the systematic synthesis of multiplier-less FIR filters with a novel complexity-aware quantization algorithm. Both signed-digit representations and common subexpression elimination (CSE) are investigated to reduce the computational complexity at the bit level. For comparable filter responses, the simulation shows that our approach requires only half (49.06%similar to50.94%) additions of the straightforward quantized filters. Both with CSE, our FIR synthesizer has comparable results with the CSD-encoded coefficients, which have the theoretically minimum non-zero terms. Moreover, our approach outperforms CSD in most cases because of the direct control over additions and the zero-overhead insertion of non-zero terms.
Complexity-aware design of DA-based fir filters
(2004)
Chen, CC
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Lin, TJ
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Liu, CW
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Jen, CW
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電子工程學系及電子研究所
This paper presents a novel technique to reduce the area of the hardwired lookup table (LUT) of DA-based FIR filters. It explores the optimal quantization on the real-valued LUT with optimal global scaling and error distribution, and we apply an effective error measure to estimate the quantization error on the FIR coefficients. Our approach enables designers to explicitly trade the quality for simple implementations at finer granularity than that solely by reducing the coefficient wordlengths. Moreover, in our simulations, the proposed method can save 30%similar to 40% silicon area of conventional DA-based FIR filters under identical error constraints.
Data stream generation for concurrent computation in VLSI signal processors
(2000)
Lin, TJ
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Jen, CW
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
Signal processing usually requires extremely high computing power. Fortunately, with advance in VLSI technology, the required performance could be achieved with more functional units performing concurrent computations on a chip. Supplying demanding data streams to these computational units soon becomes the system-performance bottleneck because of slow off-chip I/O and memory with less improvement speed. We have proposed a data stream generation (DSG) scheme that explores data reuse property existing in most signal processing algorithms while supplying appropriate data sequences. This scheme can make the VLSI signal processors much more latency and cost efficient. In the illustrating example, our DSG supplies the specified streams with 4-cycle setup time at the beginning (latency), instead of 48 cycles for each block in conventional FIFO approaches and only requires 1/6-storage elements.
Hierarchical instruction encoding for VLIW digital signal processors
(2005)
Liu, CH
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Lin, TJ
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Chao, CM
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Hsiao, PC
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Lin, LC
VLIW-based architectures are very popular in high-performance DSP processors, for their relatively simpler implementations and more predictable execution times. But they need more program memory because of (1) the fixed-length instruction encoding, (2) NOP insertion due to limited parallelism, and (3) repetitive codes for loop unrolling. This paper describes a novel hierarchical instruction encoding that address these three problems to improve the VLIW code density. In our simulations, the proposed encoding scheme saves 61.4%-66.9% code sizes in highly parallel DSP kernels, and more savings can be expected for general programs. Besides, a simple decoding architecture is proposed and has been integrated into a 4-way VLIW DSP processor. The prototype is implemented in the 0.18um CMOS technology with its operating frequency at 208MHz.
Lightweight arithmetic units for VLSI digital signal processors
(2005)
Ou, SH
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Lin, TJ
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Lin, HY
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Chao, CM
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Liu, CW
This paper presents a lightweight arithmetic for embedded signal processing, whose hardware complexity is similar to that of the integer one. In our simulations, its 16-bit version has 40.18dB signal to round-off error ratio over the IEEE single-precision floating-point arithmetic, which even out-performs the hand-optimized 32-bit code with integer arithmetic.
Novel programmable digital signal processor for multimedia applications
(2004)
Lin, LC
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Lin, TJ
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Lee, CC
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Chao, CM
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Chen, SK
This paper presents a novel DSP architecture for multimedia applications. The DSP core is a simple RISC processor from the programmer's view, which has a high-performance DSP unit and the applications can be easily targeted on the RISC shell to reduce the development time. Moreover, the DSP unit is itself a fully-programmable 4-way VLIW datapath, which has a novel ping-pong register file. To smooth the instruction execution of the two-level programmable DSP processor and improve the code density, we propose a hierarchical encoding scheme for variable-length instructions. The simulations show that our DSP has comparable performance with state-of-the-art DSP architectures, and the hierarchical instruction encoding saves 31%-64% code sizes compared to the fixed-length instruction encoding.
Performance evaluation of ring-structure register file in multimedia applications
(2003)
Lin, TJ
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Chang, CC
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Yang, TH
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Chang, YM
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Lin, CH
As the concurrent functional units in media processors increase continuously to meet the performance needs, the required access (i.e. read or write) ports of the centralized register file (RF) multiply rapidly and cannot be efficiently implemented. We propose a novel ring-structure RF, which is composed of register sub-blocks identical to the RF for a single functional unit. Data exchanges among functional units occur on the switch network of the ring registers. The proposed RF has been integrated into a four-way VLIW DSP processor successfully that demonstrates its effectiveness in DSP kernels. The synthesis result shows that our proposed ring-structure RF saves 91.88% silicon area of the centralized one, while reducing its access time by 77.35%.
Pipelining technique for energy-aware datapaths
(2005)
Huang, WS
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Lin, TJ
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Ou, SH
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Liu, CW
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Jen, CW
This paper presents a novel method to improve the energy awareness of the pipelined datapaths for varying throughputs. It activates the pipeline registers only when necessary; i.e. a data item can bypass the pipeline registers when the operation is free of race from the succeeding one, and when the glitch is minimal. Then, the clock pulses of the unused pipeline registers are gated to reduce the energy dissipation. Compared to the conventional clock gating approach, our proposed on-demand pipelining eliminates all redundant clock pulses whenever the peak datarate is not reached. Moreover, our method has a constant input-to-output latency for all operation modes, which significantly simplifies the integration tasks. In our simulations, the proposed on-demand pipelining saves up to 80% energy of conventional pipelined datapaths, and it can reduce about 34%-39% energy dissipation of those with gated-clock only.