Browsing by Author "Lin, Tay-Jyi"

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A 0.48V 0.57nJ/Pixel Video-Recording SoC in 65nm CMOS
(2013-01-01)
Lin, Tay-Jyi
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Chien, Cheng-An
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Chang, Pei-Yao
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Chen, Ching-Wen
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Wang, Po-Hao
A 52mW 1200MIPS compact DSP for multi-core media SoC
(2006)
Ou, Shih-Hao
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Lin, Tay-Jyi
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Huang, Chao-Wei
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Kuo, Yu-Ting
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Chao, Chie-Min
This paper presents a DSP core for multi-core media SoC, which is optimized to execute a set of signal processing tasks very efficiently. The fully-programmable core has a data-centric instruction set and a corresponding latency-insensitive microarchitecture, where the hardware design is optimized concurrently with its automatic software generator. The proposed DSP core has 3X performance (in cycles) of those found in commercial dual-core application processors with similar computing resources. The silicon implementation in UMC 0.18 mu m 1P6M CMOS technology operates at 314MHz and consumes only 52mW average power.
A controllable low-power dual-port embedded SRAM for DSP processor
(2008)
Yang, Hao-I
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Chang, Ming-Hung
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Lin, Tay-Jyi
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Ou, Shih-Hao
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Deng, Siang-Sen
In this paper, a low-power embedded memory module is designed for a multi-threaded DSP processor. A codesign of circuit and architecture technique is proposed. The technique includes three circuit schemes: controllable precharged bit-line, low voltage bit-line, and controllable data-retention power gating. Because the low-power control signals are generated by the DSP engine, the operating condition of the memory module can be arbitrarily adjusted by using software programming. The integration of low-power dual-port 8KB SRAM and the multi-threaded DSP engine is implemented in TSMC 130nm CMOS technology. By using these techniques, the overall access power reduction of the DSP core is around 15.30%-16.84%.
Accelerating R Data Analytics in IoT Edge Systems by Memory Optimization
(2017-01-01)
Liou, De-Yin
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Chen, Chien-Chih
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Chen, Tien-Fu
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Lin, Tay-Jyi
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資訊工程學系
With the number and variety of IoT devices increasing, a large amount of data have to be moved to the cloud, resulting into unpredictable latency from limitation of network bandwidth. R language, the most popular analytic tool, has a serious bottleneck, memory garbage collection, which will become even worse problem at the edge systems with limited memory resources. Processing a large amount of dynamic objects and high percentage of LLC misses with significantmiss penalty are the two key issues in the R execution environment. In this paper, we propose a Partially Parallel Garbage Collection to improve the waiting time during garbage collection; and a centralized memory allocation mechanism to reduce miss penalty that is caused by the high percentage of LLC misses. Our optimizations can bring benefits to those machine learning algorithms that spend most of time in R for processing large data list at the edge systems.
Adaptive Variable-Latency Cache Management for Low-Voltage Caches
(2014-01-01)
Yu, Yung-Hui
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Wang, Po-Hao
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Chen, Tien-Fu
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Lin, Tay-Jyi
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Wang, Jinn-Shyan
Scaling down the supply voltage for embedded SoC becomes a necessary technique to lower power requirements in mobile devices. However, caches become susceptible or even fail in low voltages, and distribution of access latencies is significantly increased in new technology nodes. Past researches suggested several solutions to deal with the memory reliability at low voltages, where a timing table records cache lines with latency faults. This paper proposes cache management strategies for variable-latency caches at low voltages. We analyze the locality effect and propose two methods to dynamically adapt latency faults at run time and give the advantages of those methods compared to traditional LRU for low-voltage caches.
Complexity-Aware Quantization and Lightweight VLSI Implementation of FIR Filters
(2011)
Kuo, Yu-Ting
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Lin, Tay-Jyi
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Liu, Chih-Wei
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
The coefficient values and number representations of digital FIR filters have significant impacts on the complexity of their VLSI realizations and thus on the system cost and performance. So, making a good tradeoff between implementation costs and quantization errors is essential for designing optimal FIR filters. This paper presents our complexity-aware quantization framework of FIR filters, which allows the explicit tradeoffs between the hardware complexity and quantization error to facilitate FIR filter design exploration. A new common subexpression sharing method and systematic bit-serialization are also proposed for lightweight VLSI implementations. In our experiments, the proposed framework saves 49% similar to 51% additions of the filters with 2's complement coefficients and 10% similar to 20% of those with conventional signed-digit representations for comparable quantization errors. Moreover, the bit-serialization can reduce 33% similar to 35% silicon area for less timing-critical applications.
Complexity-effective auditory compensation for digital hearing aids
(2008)
Kuo, Yu-Ting
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Lin, Tay-Jyi
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Chang, Wei-Han
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Li, Yueh-Tai
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Liu, Chih-Wei
This paper describes a complexity-effective design of auditory compensation, which is the most important building block in digital hearing aids. A multi-rate architecture and the filter bank design thereof are proposed to significantly reduce the data rates of the band-limited channels and thus the computational complexity. Several optimizations are discussed to further simplify the implementation of the dynamic range compressors in the multi-rate auditory compensation. In an 18-band 24-KHz digital hearing aid, 94% multiplications and additions are saved from a straightforward filter bank design. Moreover, the computation and memory requirements of the dynamic range compressor of each band are reduced to only 16% and 1% respectively.
Complexity-Effective Dynamic Range Compression for Digital Hearing Aids
(2010)
Chang, Kuo-Chiang
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Kuo, Yu-Ting
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Lin, Tay-Jyi
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Liu, Chih-Wei
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電子工程學系及電子研究所
Dynamic range compression (DRC) is an essential function in digital hearing aids, which have stringent power consumption constraints. This work minimized the complexity of the DRC algorithm through adopting functional approximation for those involved nonlinear operations. The tradeoff between computation reduction and approximation error was explored for reducing hardware cost without introducing audible artifact. Moreover, finite wordlength analysis is conducted for the wordlength minimization and further complexity saving. The experimental result shows that our design totally reduces 96% computing complexity of the straightforward implementation without introducing audible difference in the output signals. Compared with other approximation methods, our design also requires lower hardware complexity.
Cross-matching caches: Dynamic timing calibration and bit-level timing-failure mask caches to reduce timing discrepancies with low voltage processors
(2016-06)
Wang, Po-Hao
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Tsai, Shang-Jen
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Tanjung, Rizal
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Lin, Tay-Jyi
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Wang, Jinn-Shyan
Voltage scaling is an effective technique to reduce power consumption in processor systems. Unfortunately, timing discrepancies between L1 caches and cores occur with the scaling down of voltage. These discrepancies are primarily caused by the severe process variations of a few slow SRAM cells. Most previous designs tolerated slow cells by adjusting access latency based on a coarse-grained track of cache blocks. However, these methods become insufficient when the amount of slow cells increases. This paper addresses the issue for an 8T SRAM cache and proposes a cross-matching cache that includes dynamic timing calibration and actual bit-level timing-failure toleration. (C) 2016 Elsevier B.V. All rights reserved.
Design and implementation of a high-performance and complexity-effective VLIW DSP for multimedia applications
(2008-06-01)
Lin, Tay-Jyi
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Chen, Shin-Kai
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Kuo, Yu-Ting
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Liu, Chih-Wei
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Hsiao, Pi-Chen
This paper presents the design and implementation of a novel VLIW digital signal processor (DSP) for multimedia applications. The DSP core embodies a distributed & ping-pong register file, which saves 76.8% silicon area and improves 46.9% access time of centralized ones found in most VLIW processors by restricting its access patterns. However, it still has comparable performance (estimated in cycles) with state-of-the-art DSP for multimedia applications. A hierarchical instruction encoding scheme is also adopted to reduce the program sizes to 24.1 similar to 26.0%. The DSP has been fabricated in the UMC 0.13 mu m 1P8M Copper Logic Process, and it can operate at 333 MHz while consuming 189 mW power. The core size is 3.2 x 3.15 mm(2) including 160 KB on-chip SRAM.
Design and Implementation of Low-Power ANSI S1.11 Filter Bank for Digital Hearing Aids
(2010-07-01)
Kuo, Yu-Ting
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Lin, Tay-Jyi
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Li, Yueh-Tai
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Liu, Chih-Wei
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電子工程學系及電子研究所
Due to well matching the frequency characteristics of human ears, ANSI S1.11 1/3-octave filter bank is popular in acoustic applications, such as acoustic analyzers and equalizers. It is also desirable in hearing aids because the famous hearing aid prescription formula, NAL-NL1, prescribes its gains at ANSI 1/3-octave frequencies. However, the high computation complexity limits its usage, in which the power consumption is a critical concern. To address this issue, a low-power design and implementation of ANSI S1.11 filter bank for digital hearing aids is present. We first develop the complexity-effective multirate FIR filter bank algorithm. And, a systematic coefficient design flow is elaborated for the proposed filter bank to minimize the order of the FIR filter thereof. In an 18-band digital hearing aid with 24-kHz sampling rate, the proposed algorithm saves about 96% of multiplications and additions, comparing that with a straightforward FIR filter bank. Moreover, various low-power VLSI design techniques are investigated in detail and applied on our design. The proposed complexity-effective ANSI S1.11 FIR filter bank has been implemented in the TSMC 0.13-mu m CMOS technology with an area-efficient architecture. The test chip consumes only 87 mu W, which is 30%-79% of that of the others available in the literature. The proposed low-power ANSI 1/3-octave bank makes itself being able to precisely apply the prescribed gains obtained by NAL-NL1 prescription formula for hearing-impaired people.
Design of ANSI S1.11 filter bank for digital hearing aids
(2007)
Kuo, Yu-Ting
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Lin, Tay-Jyi
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Li, Yueh-Tai
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Chang, Wei-Han
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Liu, Chih-Wei
Existing digital hearing aids, to our knowledge, all exclude ANSI S1.11-compliant filter banks because of the high computational complexity. Most ANSI S1.11 designs are IIR-based and only applicable in applications where linear phase is not important. This paper presents an FIR-based ANSI S1.11 filter bank for digital hearing aids, which adopts a multi-rate architecture to reduce the data rates on the bandwidth-limited bands. A systematic way is also proposed to minimize the FIR orders thereof In an 18-band digital hearing aid with 24 kHz input sampling rate, the proposed design with linear phase has comparable computational complexity with IIR filter banks. Moreover, our design requires only 4% multiplications and additions of a straightforward FIR implementation.
Improving datapath utilization of programmable DSP with composite functional units
(2008)
Ou, Shih-Hao
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Cho, Yi
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Lin, Tay-Jyi
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Liu, Chih-Wei
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電子工程學系及電子研究所
A scalar (single-issue) processor executes one instruction at a time and its functional units (ALU, multiplier, and shifter, etc) are never concurrently exercised. Modem processors issue multiple instructions simultaneously (i.e. superscalar or VLIW) to improve their functional unit utilization but the cost is considerably high. In this paper, an alternative is described to activate multiple functional units concurrently by issuing a composite instruction on cascaded functional units. Besides, an automatic generator for application-specific composite functional units is presented. In our simulation with popular DSP applications, 35% increase on the operations per cycle ran be simply obtained with identical functional units. Moreover, our proposed approach saves up to 16.5% and 31.6% power on scalar and VLIW respectively for comparable performance.
Low-Cost Low-Power Droop-Voltage-Aware Delay-Fault-Prevention Designs for DVS Caches
(2015-01-01)
Chou, Pei-Yuan
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Wu, I-Chen
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Lin, Jai-Wei
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Lin, Xuan-Yu
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Chen, Tien-Fu
We propose to use a canary circuit with dynamic trip-point sensing scheme to replace ECC check bits and related circuits in conventional DVS caches for reducing area overhead and to enable deeper voltage scaling for reducing power consumption. With the canary circuit, a variable-cycle access controller can easily deal with an overlong delay without pre-allocating Vcc headroom for covering the droop voltage. Applying all the proposed delay-fault-prevention design techniques together can lead to a cost-effective and power-efficient DVS cache.
Low-Power ANSI S1.11 Filter Bank for Digital Hearing Aids
(2008)
Kuo, Yu-Ting
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Lin, Tay-Jyi
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Li, Yueh-Tai
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Lin, Chou-Kun
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Liu, Chih-Wei
This paper presents a low-power filter bank design for digital hearing aids, which is compliant with the ANSI S1.11 standard. A multi-rate filtering algorithm and its coefficient design method are proposed, which reduce 94% multiplications. The power dissipation is further reduced by 31% and 35% with switch activity reduction and multi-VDD silicon implementation respectively. The design has been implemented using the TSMC 0.13 mu m CMOS technology and consumes only 79 mu W for 24KHz 18-band audio processing.
Maintaining Color Fidelity for Dual-Shot HDR Imaging
(2014-01-01)
Yeh, Chingwei
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Tsai, Chen-Yao
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Lin, Tay-Jyi
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Guo, Juin-In
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交大名義發表
HDR synthesis using the minimal number of source images is crucial for real-time applications. This paper identifies the color distortion problem associated with the minimum of two source images, and proposes a solution using the virtual frame composed in the pixel domain. Experimental results demonstrate satisfactory results.
Method for inter-cluster communication that employs register permutation
(2005-09-15)
Jen, Chein-Wei
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Lin, Tay-Jyi
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Lee, Chen-Chia
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Chang, Chin-Chi
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Liu, Chih-Wei
The present invention is a method for inter-cluster communication that employs register permutation by dynamically mapping the registers to the functional units. Because only the mapping between registers and functional units is changed and no actual data movement occurs, the present invention greatly diminishes the power consumption. Owing to the inter-cluster communication mechanism, a centralized register file can be replaced with small register sub-blocks, where the silicon area is greatly reduced, and the access time and the power consumption are also diminished.
MULTITASKING PROCESSOR AND TASK SWITCHING METHOD THEREOF
(2010-02-25)
Lin, Tay-Jyi
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Huang, Pao-Jui
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Liu, Chih-Wei
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Chen, Shin-Kai
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Wang, Bing-Shiun
A multitasking processor and a task switching method thereof are provided. The task switching method includes following steps. A first task is executed by the multitasking processor, wherein the first task contains a plurality of switching-point instructions. An interrupt event occurs. Accordingly, the multitasking processor temporarily stops executing the first task and starts to execute a second task. The multitasking processor executes a handling process of the interrupt event and sets a switching flag. After finishing the handling process of the interrupt event, the multitasking processor does not perform task switching but continues to execute the first task, and the multitasking processor only performs task switching to execute the second task when it reaches a switching-point instruction in the first task.
Multithreaded coprocessor interface for multi-core multimedia SoC
(2008)
Ou, Shih-Hao
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Lin, Tay-Jyi
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Deng, Xiang Sheng
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Zhuo, Zhi Hong
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Liu, Chih Wei
Modern architectures exploit task level parallelism to improve their performance in a cost-effective manner. However, task synchronization and management Is time consuming and wastes computing resources especially on application-specific architectures, such as DSP. In this paper, we propose a smart coprocessor interface that helps to offload the task management job from MPU or DSP. In our simulations, our approach can improve the overall performance of a dual-core platform by 57%. The hardware overhead of the interface is only 1.56% of the DSP core.
Parallel Architecture Core (PAC)-the First Multicore Application Processor SoC in Taiwan Part I: Hardware Architecture & Software Development Tools
(2011-03-01)
Chang, David Chih-Wei
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Lin, Tay-Jyi
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Wu, Chung-Ju
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Lee, Jenq-Kuen
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Chu, Yuan-Hua
In order to develop a low-power and high-performance SoC platform for multimedia applications, the Parallel Architecture Core (PAC) project was initiated in Taiwan in 2003. A VLIW digital signal processor (PACDSP) has been developed from a proprietary instruction set with multimedia-rich instructions, a complexity-effective microarchitecture with an innovative distributed & ping-pong register organization and variable-length VLIW encoding, to a highly-configurable soft IP with several successful silicon implementations. A complete toolchain with an optimizing C compiler has also been developed for PACDSP. A dual-core PAC SoC has been designed and fabricated, which consists of a PACDSP core, an ARM9 core, scratchpad memories, and various on-chip peripherals, to demonstrate the outstanding performance and energy efficiency for multimedia processing such as the real-time H.264 codec. The first part of the two introductory papers of PAC describes the hardware architecture of the PACDSP core, its software development tools, and the PAC SoC with dynamic voltage and frequency scaling (DVFS).