Browsing by Author "Lin, Tingyou"

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High-R Poly Resistance Deviation Improvement From Suppressions of Back-End Mechanical Stresses
(2017-10-01)
Lin, Tingyou
;
Ho, Yingchieh
;
Su, Chauchin
;
電機工程學系
;
電信工程研究所
This paper investigates techniques for N-type high-resistance polysilicon resistors to reduce the resistance deviation which is caused by the back-end mechanical stress. In the back-end layers of the wafer, a top metal thickness equal to 3 mu m is provided to increase the heat allowing current density in the metal routes of power ICs. The top metal processing yields the mechanical stress to increase the resistance by the piezoresistance effect. To eliminate the mechanical stresses, a new layout is proposed with the full passivation cutting (FPC). The resistor with an FPC uses the passivation film separation to create a physical empty room for suppressing the mechanical stresses on the polysilicon. The proposed layout has been verified in the 0.4-mu m bipolar-CMOS-DMOS process, and the resistance shifts were compared with other four-type layouts. Compared to those original layouts, the proposed layout exhibits the improvements in the resistance deviation reduction in the maximum ratio 20.80%.
Improving Safe-Operating-Area o f a 5-V n-Channel Large Array MOSFET in a 0.15-mu m BCD Process
(2018-07-01)
Nidhi, Karuna
;
Ker, Ming-Dou
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Lin, Tingyou
;
Lee, Jian-Hsing
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資訊工程學系
The safe-operating-area (SOA) of large array device (LAD) is one of the most important factors affecting the device reliability. In this paper, the improvement of the electrical-SOA (E-SOA) and the thermal-SOA (T-SOA) by using an optional implantation layer for 5-V n-channel large array MOSFET has been investigated in a 0.15-mu m bipolar-CMOS-DMOS process. Experimental results showed that the secondary breakdown current (It2) is improved by 5 times, and a significant improvement is also observed in the E-SOA and the T-SOA boundary as compared to the original device. In addition, the impact of inserting additional layout pick-ups into the multiple-finger layout of large array MOSFET to the E-SOA, It2, and trigger voltage is also practically investigated in silicon for the LAD with a total width of 12000 mu m.
LDMOS Channel Thermometer Based on a Thermal Resistance Sensor for Balancing Temperature in Monolithic Power ICs
(2017-06-01)
Lin, Tingyou
;
Ho, Yingchieh
;
Su, Chauchin
;
電子工程學系及電子研究所
;
電信工程研究所
This paper presents a method of thermal balancing for monolithic power integrated circuits (ICs). An on-chip temperature monitoring sensor that consists of a poly resistor strip in each of multiple parallel MOSFET banks is developed. A temperature-to-frequency converter (TFC) is proposed to quantize on-chip temperature. A pulse-width-modulation (PWM) methodology is developed to balance the channel temperature based on the quantization. The modulated PWM pulses control the hottest of metal-oxide-semiconductor field-effect transistor (MOSFET) bank to reduce its power dissipation and heat generation. A test chip with eight parallel MOSFET banks is fabricated in TSMC 0.25 mu m HV BCD processes, and total area is 900 x 914 mu m(2). The maximal temperature variation among the eight banks can reduce to 2.8 degrees C by the proposed thermal balancing system from 9.5 degrees C with 1.5 W dissipation. As a result, our proposed system improves the lifetime of a power MOSFET by 20%.
Package and Chip Accelerated Aging Methods for Power MOSFET Reliability Evaluation
(2019-01-01)
Lin, Tingyou
;
Su, Chauchin
;
Hung, Chung-Chih
;
Nidhi, Karuna
;
Tu, Chily
This paper investigates power MOSFET stress strategies for both package and chip aging evaluation. Two stress test methods are developed to speed up packaging and chip aging process respectively. As a result, the characteristics shifts of package and chip aging can be plotted independently. Thus, the measurement accuracy and measurement time can be improved. A test chip is designed and fabricated in a 0.15tm BCD process. The measured results demonstrate a 10kjtm power MOSFET has R-on increased by 72% after 6.3hr stress for the package aging. For the chip aging, the MOSFET has R-on increased by 12% after 600 times stress pulses. The measurement verifies that the accelerated aging in the package and the chip can be controlled separately.