Browsing by Author "Lin, W. L."

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Analysis and Realization of TLC or even QLC Operation with a High Performance Multi-times Verify Scheme in 3D NAND Flash memory
(2018-01-01)
Lu, C. C.
;
Cheng, C. C.
;
Chiu, H. P.
;
Lin, W. L.
;
Chen, T. W.
Feasibility of multi-times verify (MTV) scheme on triple-level cell (TLC) and quad-level cell (QLC) operations of charge-trap storage 3D NAND memories is investigated comprehensively. Results reveal that random telegraph noise (RTN) and program noise are the major factors affecting lower (LB) and upper boundaries (HB) of Vt distribution, respectively. Enlargement of operation window and reduction of ECC usage with MTV scheme to mitigate RTN-induced LB tail are demonstrated on TLC and QLC operations. In addition, the impact of program noise on HB Vt under various process conditions and ISPP steps is studied experimentally and also explained by our Monte Carlo simulator. Finally, program performance and reserved margin with and without MTV scheme applied on TLC and QLC operation are demonstrated.
Polycrystalline-Silicon Channel Trap Induced Transient Read Instability in a 3D NAND Flash Cell String
(2016-01-01)
Tsai, Wen-Jer
;
Lin, W. L.
;
Cheng, C. C.
;
Ku, S. H.
;
Chou, Y. L.
Vt instability caused by grain-boundary trap (GBT) in the poly-crystalline silicon (poly-Si) channel of a 3D NAND string are comprehensively studied. Experimental results reveal that trapping/detrapping of GBT would cause transient cell current with a time constant of lOus or longer, and this transient is strongly affected by the bias history. Sensing offset between program/erase verify (PV/EV) and read (RD) results in "pseudo" charge loss/gain that reduces the sensing margin. Modified EV, PV, or RD bias schemes are suggested to mitigate this effect.