Browsing by Author "Lin, Wei-Tin"

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Dynamic-Charging Current-Scaling Technique with Dual Accurate Current Control and Temperature Loops with Charging-Current Accuracy up to 99.6% for 1.6x Faster Lithium-Ion Battery Charging
(2019-01-01)
Lin, Wei-Tin
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Lin, Zong-Yi
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Liu, Chia-Hao
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Huang, Chia-Ming
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Chu, Li-Cheng
Non-Slicing Floorplanning-Based Crosstalk Reduction on Gridless Track Assignment for a Gridless Routing System with Fast Pseudo-Tile Extraction
(2008)
Chang, Yu-Ning
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Li, Yih-Lang
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Lin, Wei-Tin
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Cheng, Wen-Nai
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資訊工程學系
Track assignment, which is an intermediate stage between global routing and detailed routing, provides a good platform for promoting performance, and for imposing additional constraints during routing, such as crosstalk. Gridless track assignment (GTA) has not been addressed in public literature. This work develops a gridless routing system integrating a congestion-driven global router, crosstalk-driven GTA and an enhanced implicit connection-graph-based router. Initial assignment is produced rapidly with a left-edge like algorithm. Crosstalk reduction on the assignment is then transformed to a restricted non-slicing floorplanning problem, and a deterministic O-tree based algorithm is employed to re-assign each net segment. Finally, each panel is partitioned into several sub-panels, and the sub-panels are re-ordered using branch and bound algorithm to decrease the crosstalk further. Before detailed routing, routing tree construction is undertook for placed IRoutes and other pins; many original point-to-point routings are set to connect to IRoutes, and can be accomplished simply with pattern routing. For detailed routing, this work proposes a rapid extraction method for pseudo-maximum stripped tiles to boost path propagation. Experimental results demonstrate that the proposed gridless routing system has over 2.66 times the runtime speedup for fixed- and variable-rule routings of an implicit connection-graph-based router, NEMO. As compared with a commercial routing tool, this work yields an average reduction rate of 15% in coupling capacitance calculated using its built-in coupling capacitance estimator.
Pseudo AC Current Synthesizer and DC Offset-Corrected Technique in Constant-on-time Control Buck Converter for Werable Electronics
(2015)
Su, Jui-Che
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Chen, Wei-Chung
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Lin, Wei-Tin
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Chou, Ying-Wei
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Chien, Meng-Wei
Constant-on-time (COT) control with an additional current feedback in conventional buck converter has the advantage of using low equivalent series resistance (ESR) output capacitor. Unfortunately, the disadvantage is output voltage regulation accuracy is greatly deteriorated by its DC offset voltage from the current feedback. More seriously, opposite reaction between output voltage and the additional current feedback signal deteriorates transient response. In this paper, pseudo AC current synthesizer and DC voltage offset correction technique are proposed to reduce load-dependent DC offset voltage for improving load regulation. Furthermore, the transient enhancement technique instantly extends on-time and the off-time periods in load change. Test chip fabricated in UMC 28nm CMOS process demonstrated that offset voltage is improved from 65mV to 4mV. Besides, the transient response can be improved to 4 mu s and 5 mu s when load changes from 0.3 to 1.7A and vice versa, respectively. The advantages of compact size, low cost, and high performance power management can maintain wearable electronics small volume, light, and sustainable.