Browsing by Author "Lin, YN"

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A chip-interleaved synchronous DS-CDMA technique enabling MAI-free and reduced-ISI transmission with low complexity receiving
(2004)
Lin, YN
;
Lin, DW
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The capacity of conventional direct-sequence code-division multiaccess (DS-CDMA) systems is limited by multiaccess interference (MAI) that arises from correlation among user signals, especially in multipath channels. While inducing an intersymbol-interference (ISI) problem, chip-interleaved DS-CDMA (CIDS-CDMA) can preserve the orthogonality among user signals and effect MAI-free transmission. We propose a multicode CIDS-CDMA (MCIDS-CDMA) technique which can also remove ISI in addition to MAI when a sufficient number of multicodes are assigned. This design facilitates a low complexity receiver structure. In addition, a low complexity ISI canceller can be used to deal with the residual ISI, should the number of codes be insufficient.
Analysis of hardlimiting parallel interference cancellation (PIC) for synchronous CDMA communication
(2002)
Lin, YN
;
Lin, DW
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Parallel interference cancellation (PIC) is a widely considered approach to multiuser detection in CDMA communication. While PIC receivers normally involve nonlinear functions, previous performance analyses mainly addressed linear PIC. We find that the performance of purely hardlimiting PIC may not improve after the second stage. In addition, for the two-user case, one stage usually suffices. Further, the performance of hardlimiting PIC does not approach the single-user limit. We also develop approximate expressions for numerical evaluation of the hardlimiting PIC performance. Simulation results agree well with the analysis.
Chip interleaving for performance improvement of coded DS-CDMA systems in Rayleigh fading channels
(2003)
Lin, YN
;
Lin, DW
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In mobile wireless communication, signal is usually subject to fading. Gain-combining diversity is a common remedy for fading effects. Practical channel coded direct-sequence code-division-multiple-access (DS-CDMA) uses bit interleaving to effect gain-combining time diversity through the redundancy provided by the channel code. Recently, some have proposed chip-interleaved DS-CDMA (CIDS-CDMA). Simple CIDS-CDMA considers a set of bits at a time. Similarly indexed chips in the bits are grouped together for transmission. Such interleaving has been shown to yield diversity gain in uncoded transmission. This paper considers the performance of CIDS-CDMA with channel coding. For simplicity, synchronous DS-CDMA is considered. In addition to simple CIDS-CDMA, we also consider combined bit-and-chip interleaving (BODS-CDMA). We present theoretical analysis and simulation results for both cases under long-code and short-code spreading. It is concluded that the code period is vital for simple CIDS-CDMA but is of no importance for BCIDS-CDMA. Another conclusion is that BCIDS-CDMA yields the best performance for it provides the largest diversity gain.
Chip-interleaved WCDMA with parallel-interference-cancellation receiver in multipath Rayleigh fading channels
(2004)
Lin, YN
;
Lin, DW
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Multiple access interference (MAI) is a major limiting factor of DS-CDMA system capacity. Parallel interference cancellation (PIC) is an effective means to mitigate MAI. However, if the initial decisions of which PIC is based on have high error probabilities, then PIC cannot perform well. To improve the performance of PIC, we propose chip-interleaving to provide intra-bit diversity. Then the initial decisions can be more accurate so as to enhance the PIC's performance. We design a chip-interleaving scheme based on some 3GPP WCDMA system features, such as the use of the Q-branch to transmit control bits and the I-branch to transmit data bits in a QPSK-like modulation scheme. Simulation results show that the proposed chip-interleaved WCDMA (CI-WCDMA) transmission can have significant performance advantage compared to simple WCDMA in transmission over fading multipath channels with MAI.
DiffServ edge routers over network processors: Implementation and evaluation
(2003-07-01)
Lin, YD
;
Lin, YN
;
Yang, SC
;
Lin, YS
;
資訊工程學系
Network processors are emerging as a programmable alternative to the traditional ASIC-based solutions in scaling up the data plane processing of network services. This work, rather than proposing new algorithms, illustrates the process of, and examines the performance issues in, prototyping a DiffServ edge router with IXP1200. The external benchmarks reveal that although the system can scale to wire speed of 1.8 Gb/s in simple IP forwarding, the throughput declines to 180-290 Mb/s when. DiffServ is performed due to the double bottlenecks of SRAM and microengines. Through internal benchmarks, the performance bottleneck was found to be able to shift from one place to another en different network services and algorithms. Most of the results reported here should be applicable to other NPs since they have similar architectures and components.
DiffServ over network processors: Implementation and evaluation
(2002)
Lin, YD
;
Lin, YN
;
Yang, SC
;
Lin, YS
;
資訊工程學系
Network processors are emerging as a programmable alternative to the traditional ASIC-based solutions in scaling up the data-plane processing of network services. This work, rather than proposing new algorithms, illustrates the process of and examines the performance issues in, prototyping a DiffServ edge router with IXP1200. The external benchmarks reveal that though the system can scale to wire-speed of 1.8Gbps in simple IP forwarding, the throughput declines to 180Mbpssimilar to290Mbps when DiffServ is performed due to the double bottlenecks of SRAM and microengines. Through internal benchmarks, the performance bottleneck was found to be able to shift from one place to another given different network services and algorithms. Most of the result reported here shall remain the same for other NPs since they have similar architectures and components.
Discovery of different types of inhibition between the human and Thermotoga maritima alpha-fucosidases by fuconojirimycin-based derivatives
(2006-05-09)
Ho, CW
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Lin, YN
;
Chang, CF
;
Li, ST
;
Wu, YT
An efficient method for examining the selectivity of inhibitors on two alpha-fucosidases, one from Thermotoga maritima and the other from human, was established. The X-ray crystal structure of the former enzyme makes possible the homology modeling of the human alpha-fucosidase, indicating the major difference between both enzymes in the periphery of the catalytic site. To investigate the difference at the molecular level, a variety of fuconojirimycin (FNJ) derivatives with substitution at Cl, C2, C6, or N were rapidly prepared in microplates and screened without purification for the inhibition activities of the two alpha-fucosidases. Among the molecules that were tested, only the substitution at Cl can significantly enhance the inhibitory potency, in contrast to the control (no substitution) and compounds with substitution at other positions. The majority of Cl-substituted FNJs were found to be slow tight-binding inhibitors of the Thermotoga enzyme, while acting as the reversible inhibitors of the human fucosidase. The best inhibitor exhibited 13700-fold difference in affinity between the two enzymes, which was attributed to the dissimilar aglycon binding site. Further investigations were carried out, including site-directed mutagenesis, the comparison of K-i values among the wild type and mutants, and the intrinsic fluorescence change upon inhibitor titration, all supporting the idea that Tyr64 and Tyr267 of the Thermotoga alpha-fucosidase are critically involved in closely interacting with the aglycon of inhibitors. The increased level of contact thus induced conformational change, leading to the observed slow tight-binding inhibition.
DSP implementation of successive interference cancellation (SIC) receiver for 3GPP WCDMA uplink transmission
(2003-09-01)
Chang, YJ
;
Lin, YN
;
Lin, DW
;
電子工程學系及電子研究所
;
電信研究中心
The 3GPP WCDMA is a widely accepted third-generation cellular system standard. By using nonorthogonal codes for different users. the Multiple access interference (MAI) can be a limiting factor for system performance, as for other CDMA systems. Multiuser detection (MUD) is known to reduce MAI and improve CDMA system performance. but many Such techniques have high complexity. Successive interference cancellation (SIC) is an effective MUD technique with relatively low complexity. We consider the software implementation of an SIC receiver for WCDMA uplink transmission on a commercially available general-purpose multi digital signal processor (DSP) platform. This also goes in line with the recent interest in software-defined radio. Issues addressed in this work include job partitioning and signal routing for multiprocessor implementation, design of SIC components (especially the channel estimator and the si mal regenerator), determination of the precision of fixed-point computations. consideration of the receiver's error performance and analysis of the implementation's complexity and efficiency. These issues are tightly coupled with the 3GPP WCDMA specifications. Because the employed platform only contains four DSPs, the implementation only considers up to three users. But this is sufficient for Lis to appreciate various DSP implementation issues of an SIC receiver. Moreover, by the nature of SIC, it is easy to extend the implementation to handle more users with an enlarged platform. Our present implementation achieves real-time speed in the RAKE receiver part of the complete receiver. Due to the complexity in signal regeneration, the overall SIC receiver still falls short of the real-time requirement when interference cancellation is activated. In fact, the platform employed presently cannot support real-time processing when the number of multipaths is four or more, unless either the system architecture or the SIC algorithm is redesigned. Such and other ways of improvement are relegated to potential future work. Copyright (C) 2003 John Wiley Sons, Ltd.
Multiple access over fading multipath channels employing chip-interleaving code-division direct-sequence spread spectrum
(2003-01-01)
Lin, YN
;
Lin, DW
;
電子工程學系及電子研究所
;
電信研究中心
;
Department of Electronics Engineering and Institute of Electronics
Multiple access interferecnce (MAI) is a major factor limiting the performance of direct-sequence code-division multiple access (DS-CDMA) systems. Since the amount of MAI is dependent on the correlation among user signals, one way to reduce it is to reduce such correlation. In mobile multiuser communication, each user experiences a different time-varying channel response. This user-dependent characteristic in channel variation can be exploited to assist the separation of different user signals, in addition to the capability provided by the spreading codes. As the correlation among different user channels are expected to decrease with increase in time span, enhanced decorrelation among different users' signals can be effected by spacing out the chips of one modulated symbol in time. Thus we consider chip-interleaving DS-CDMA (CI-DS-CDMA) in this study. We investigate its performance through theoretical analysis and computer simulation. Employing only a slightly modified rake receiver structure, CI-DS-CDMA is shown to attain significant performance gain over conventional DS-CDMA, in multiple access communication over single- and multi-path fading channels, without complicated multiuser detection. CI-DS-CDMA also has a lower demand for short-term power control than conventional DS-CDMA, especially in one-path Rayleigh fading. Results of the theoretical analysis and the computer simulation agree well with each other.
Novel analytical results on performance of bit-interleaved and chip-interleaved DS-CDMA with convolutional coding
(2005-05-01)
Lin, YN
;
Lin, DW
;
電子工程學系及電子研究所
;
電信研究中心
;
Department of Electronics Engineering and Institute of Electronics
We present a unified performance analysis for the conventional bit-interleaved direct-sequence (DS) code-division multiple access (BIDS-CDMA) and the more recently proposed chip-interleaved DS-CDMA (CIDS-CDMA), both with channel coding. Simple CIDS-CDMA treats a set of bits at a time and interleaves their chips together for transmission. But bit interleaving may also be used on top of chip interleaving (thus abbreviated BCIDS-CDMA) to enhance performance. For simplicity, we first tackle flat-faded synchronous transmission, in which we treat both the condition with perfect power control and that where the received signal is subject to Rayleigh fading. We then extend the analysis to asynchronous and multipath channels, with the latter treated only briefly. By approximating the correlation among the spreading codes (rather than the ensuing interference) as Gaussian, we obtain novel and relatively simple results for the various conditions above. In general, BCIDS-CDMA performs best, followed by simple CIDS-CDMA and then by BIDS-CDMA. Within simple CIDS-CDMA and BIDS-CDMA, long-code spreading performs better than short-code spreading. For BCIDS-CDMA with perfect interleaving that fully randomizes the fading coefficients, the performance is not affected by the spreading code period. The above ordering of performance follows the amount of diversity each scheme exploits, where the diversity may come from spectrum spreading, channel coding, and independence in fading of different paths. Simulation results agree well with the theoretical analysis.
On optimal power distribution for successive interference cancellation (SIC) for wideband CDMA
(2001)
Lin, YN
;
Lin, DW
;
電子工程學系及電子研究所
;
電信研究中心
;
Department of Electronics Engineering and Institute of Electronics
Sucessive interference cancellation (SIG) is an effective technique to reduce multiple acess interference and thereby increase capacity. While a conventional receiver attains best performance under equal received power for all users, an SIG-based receiver favors unequal powers. In this paper, we consider ways to assign powers to the received user signals for the benefit of SIG-based multiuser detection. Two power assignment methods, both allocating user signal powers according to their sequence of detection in SIG, are investigated. Through numerical simulation, the methods are shown to greatly improve the bit error rate (BER) performance compared to equal-power assignment. The simulation results also show that, under these methods of power assignment, SIG yields superior performance to parallel interference cancellation (PIC) in high data rate transmission.
Tunnel minimization and relay for managing virtual private networks
(2004)
Chen, IW
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Lin, YD
;
Lin, YN
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資訊工程學系
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Department of Computer Science
A virtual private network (VPN) is a private data network that carries traffic between remote sites. One of the most popular VPN applications is the "Intranet/Extranet VPN", which establishes network layer connections between remote intranet sites, using various tunneling protocols, to create an IP overlay network. IPSec, which is very prevalent in industry, is one of these tunneling protocols that not only provide encapsulation/decapsulation but encryption/decryption and hashing. However, an IPSec tunnel often fails to be established due to the management complexity. This work proposes the new concept of authority to alleviate the management overhead by reducing the number of tunnels. The problem of tunnel minimization is first formalized under three conditions-no constraint, a Tunnel Path Length constraint and a Tunnel Relay Degree constraint, and then solved using graphical models and the Zero-One Integer Programming algorithm. The effect of tunnel minimization is also investigated, and at most 90% of the tunnels are found to be reducible in a general enterprise VPN.
VPN gateways over network processors: Implementation and evaluation
(2005)
Lin, YN
;
Lin, CH
;
Lin, YD
;
Lai, YC
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資訊工程學系
Networking applications, such as VPN and content filtering, demand extra computing power in order to meet the throughput requirement nowadays. In addition to pure ASIC solutions, network processor architecture is emerging as an alternative to scale up data-plane processing while retaining design flexibility. This article, rather than proposing new algorithms, illustrates the experience in developing IPSec-based VPN gateways over network processors, and investigates the performance issues. The external benchmarks reveal that the system can reach 45Mbps for IPSec using 3DES algorithm, which improves by 350% compared to single XScale core processor and parallels the throughput of a PIII IGHz processor. Through the internal benchmarks, we analyze the turnaround times of the main functional blocks, and identify the core processor as the performance bottleneck for both packet forwarding and IPSec processing.