Browsing by Author "Lin, Yi-Min"

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A 2.56 Gb/s Soft RS (255,239) Decoder Chip for Optical Communication Systems
(2014-07-01)
Lin, Yi-Min
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Hsu, Chih-Hsiang
;
Chang, Hsie-Chia
;
Lee, Chen-Yi
;
電子工程學系及電子研究所
Due to high transmission rate requirement for optical communication systems, the growing uncertainty of received signals results in the limited transmission distance. In this paper, a decision-confined soft RS decoder chip is proposed to enhance the error correcting performance with area-efficient architectures. Instead of generating numerous possible candidate codewords and determining the most likely one as output codeword, our approach produces only one codeword by confining the degree of error location polynomial. Therefore, hardware complexity is significantly reduced by eliminating decision making unit. Moreover, an iteration-reduced RiBM algorithm is provided to enlarge the coding gain by using more least reliable positions (LRPs) in the limited operation latency. According to simulation results, our proposed soft RS (255, 239; 8) decoder with 5 LRPs outperforms 0.4 dB at 10(-4) codeword error rate (CER) as compared to hard RS decoders. Implemented in standard CMOS 90 nm technology, the soft decoder chip can achieve 2.56 Gb/s throughput with similar complexity as a hard decoder. It can fit well for 10-40 Gb/s with 16 RS decoders in optical fiber systems and 2.5 Gb/s GPON applications.
A 26.9 K 314.5 Mb/s Soft (32400,32208) BCH Decoder Chip for DVB-S2 System
(2010-11-01)
Lin, Yi-Min
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Chen, Chih-Lung
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Chang, Hsie-Chia
;
Lee, Chen-Yi
;
電子工程學系及電子研究所
This paper provides a soft Bose-Chaudhuri-Hochquenghem (BCH) decoder chip with soft information from the LDPC decoder for the DVB-S2 system. In contrast with the hard BCH decoder, the proposed soft BCH decoder that deals with least reliable bits can provide much lower complexity with similar error-correcting performance. Moreover, the error locator evaluator is proposed to evaluate error locations without the Chien search for higher throughput, and the Bjorck-Pereyra error magnitude solver (BP-EMS) is presented to improve decoding efficiency and hardware complexity. The chip measurement results reveal that our proposed soft (32400, 32208) BCH decoder for DVB-S2 system can achieve 314.5 Mb/s with a gate-count of 26.9 K in standard 90 nm 1P9M CMOS technology. Extended for fully supporting 21 modes in the DVB-S2 system, our approach can achieve 300 MHz operation frequency with a gate-count of 32.4 K.
A 26.9K 314.5Mbps Soft (32400,32208) BCH Decoder Chip for DVB-S2 System
(2009)
Lin, Yi-Min
;
Chen, Chih-Lung
;
Chang, Hsie-Chia
;
Lee, Chen-Yi
;
電子工程學系及電子研究所
This paper provides a soft BCH decoder using error magnitudes to deal with least reliable bits. With soft information from the previous decoder defined in digital video broadcasting (DVB), the proposed soft BCH decoder provides much lower complexity and latency than the traditional hard BCH decoder while still maintaining performance. The proposed error locator evaluator architecture evaluates error locations without Chien search, leading to high throughput. Borck-Pereyra error magnitudes solvers (BP-EMS) is presented to improve decoding efficiency and hardware complexity. The experimental result reveals that our proposed soft (32400, 32208) BCH decoder defined in DVB-S2 system can save 50.0% gate-count and achieve 314.5Mbps in standard CMOS 90nm technology.
A compact RF CMOS modeling for accurate high-frequency noise simulation in sub-100-nm MOSFETs
(2008-09-01)
Guo, Jyh-Chyurn
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Lin, Yi-Min
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A compact RF CMOS model incorporating an improved thermal noise model is developed. Short-channel effects (SCEs), substrate potential fluctuation effect, and parasitic-resistance-induced excess noises were implemented in analytical formulas to accurately simulate RF noises in sub-100-nm MOSFETs. The intrinsic noise extracted through a previously developed lossy substrate de-embedding method and calculated by the improved noise model can consistently predict gate length scaling effects. For 65- and 80-nm n-channel MOS with f(T) above 160 and 100 GHz, NF(min) at 10 GHz can be suppressed to 0.5 and 0.7 dB, respectively. Drain current noise S(id) reveals an apparently larger value for 65-nm devices than that for 80-nm devices due to SCE. On the other hand, the shorter channel helps reduce the gate current noise S(ig) attributed to smaller gate capacitances. Gate resistance R(g)-induced excess noise dominates in S(ig) near one order higher than the intrinsic gate noise that is free from R(g) for 65-nm devices. The compact RF CMOS modeling can facilitate high-frequency noise simulation accuracy in nanoscale RF CMOS circuits for low-noise design.
A Fully Parallel BCH Codec with Double Error Correcting Capability for NOR Flash Applications
(2012)
Chu, Chia-Ching
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Lin, Yi-Min
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Yang, Chi-Heng
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Chang, Hsie-Chia
;
電子工程學系及電子研究所
A double error correcting (DEC) BCH codec is designed for NOR flash memory systems to improve reliability. Due to the latency constraint less than 10 ns, the fully parallel architecture with huge hardware cost is utilized to process both the encoding and decoding scheme within one clock cycle. Notice that encoder and decoder will not be activated simultaneously in NOR flash applications, so we combine the encoder and syndrome calculator based on the property of minimal polynomials in order to efficiently arrange silicon area. Furthermore, a new error location polynomial is developed to reduce the number of constant finite filed multipliers (CFFMs) in Chien search. According to 90 nm CMOS technology, our propose DEC BCH codec can achieve 2.5 ns latency with 41,705 mu m(2) area.
A Long Block Length BCH Decoder for DVB-S2 Application
(2009)
Lin, Yi-Min
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Wu, Jau-Yet
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Lin, Chien-Ching
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Chang, Hsie-Chia
;
電子工程學系及電子研究所
In this paper, a low-complexity and full-mode BCH decoder with long block length for DVB-S2 application is presented. With the reversed error locator polynomial, our proposed reversed Berlekamp-Massey algorithm features a sharing architecture to perform parallel-4 syndrome and Chien search calculations. Concatenated with the LDPC decoder, which has a long decoding latency and a short period of data output time, the proposed parallel-4 BCH decoder ensures the sufficient throughput with only one bank memory. Moreover, a composite field divider instead of a large Galois field inversion table is also presented to reduce complexity. After implemented in 0.13 mu m CMOS technology, our parallel-4 BCH decoder occupied 44K gate count can reach 380Mb/s according to the post-layout simulations.
A MPCN-Based Parallel Architecture in BCH Decoders for NAND Flash Memory Devices
(2011-10-01)
Lin, Yi-Min
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Yang, Chi-Heng
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Hsu, Chih-Hsiang
;
Chang, Hsie-Chia
;
Lee, Chen-Yi
According to large-page-size and random-bit-error characteristics, long-block-length Bose-Chaudhuri-Hochquenghem (BCH) decoders are applied to realize error correction in NAND Flash memory devices. To accelerate the decoding process in an area-efficient architecture, a parallel architecture with minimal polynomial combinational network (MPCN) for long BCH decoders is presented in this brief. The proposed design utilizes MPCNs to replace constant finite-field multipliers, which dominate the hardware complexity of the high-parallel Chien search architecture. Furthermore, both the syndrome calculator and the Chien search can be merged by exploiting our MPCN-based architecture, leading to significant hardware complexity reduction. From the synthesis results in the 90-nm CMOS technology, the MPCN-based joint syndrome calculation and Chien search has 46.7% gate count saving for parallel-32 BCH (4603, 4096; 39) decoder in contrast with the straightforward design.
A new lossy substrate model for accurate RF CMOS noise extraction and simulation with frequency and bias dependence
(2006-11-01)
Guo, Jyh-Chyurn
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Lin, Yi-Min
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A lossy substrate model is developed to accurately simulate the measured RF noise of 80-nm super-100-GHz f(T) n-MOSFETs. A substrate RLC network built in the model plays a key role responsible for the nonlinear frequency response of noise in 1-18-GHz regime, which did not follow the typical thermal noise theory. Good match with the measured S-parameters, Y-parameters, and noise parameters before deembedding proves the lossy substrate model. The intrinsic RF noise can be extracted easily and precisely by the lossy substrate deembedding using circuit simulation. The accuracy has been justified by good agreement in terms of I-d, g(m), Y-parameters, and f(T) under a wide range of bias conditions and operating frequencies. Both channel thermal noise and resistance induced excess noises have been implemented in simulation. A white noise gamma factor extracted to be higher than 2/3 accounts for the velocity saturation and channel length modulation effects. The extracted intrinsic NFmin as low as 0.6-0.7 d at 10 GHz indicates the advantages of super-100 GHz f(T) offered by the sub-100-nm multifinger n-MOSFETs. The frequency dependence of noise resistance R-n suggests the bulk RC coupling induced excess channel thermal noise apparent in 1-10-GHz regime. The study provides useful guideline for low noise and low power design by using sub-100-nm RF CMOS technology.
An MPCN-Based BCH Codec Architecture With Arbitrary Error Correcting Capability
(2015-07-01)
Yang, Chi-Heng
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Lin, Yi-Min
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Chang, Hsie-Chia
;
Lee, Chen-Yi
;
電子工程學系及電子研究所
This paper presents an area-efficient architecture of arbitrary error correction Bose-Chaudhuri-Hocquenghem codec for NAND flash memory. By factorizing the generator polynomial into several minimal polynomials and utilizing linear feedback shift registers based on minimal polynomials, our reconfigurable design cannot only support multiple error correcting capabilities at a few extra cost, but also merge the encoder and syndrome calculator for efficiently reducing hardware complexity. After being implemented in CMOS 65-nm technology, the test chip supporting t = 1-24 bits can achieve 1.33-Gb/s measured throughput with 73k gate-count while another design supporting t = 60-84 bits can provide 1.60-Gb/s synthesized throughput with 168.6k gate-count.
Improved High Code-Rate Soft BCH Decoder Architectures With One Extra Error Compensation
(2013-11-01)
Lin, Yi-Min
;
Chang, Hsie-Chia
;
Lee, Chen-Yi
;
電機工程學系
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Department of Electrical and Computer Engineering
Compared with traditonal hard Bose-Chaudhuri-Hochquenghem (BCH) decoders, soft BCH decoders provide better error-correcting performance but much higher hardware complexity. In this brief, an improved soft BCH decoding algorithm is presented to achieve both competitive hardware complexity and better error-correcting performance by dealing with least reliable bits and compensating one extra error outside the least reliable set. For BCH (255, 239; 2) and (255, 231; 3) codes, our proposed soft BCH decoders can achieve up to 0.75-dB coding gain with one extra error compensation and 5% less complexity than the traditional hard BCH decoders.
RF Noise Shielding Method and Modelling for Nanoscale MOSFET
(2008)
Guo, Jyh-Chyurn
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Lin, Yi-Min
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Tsai, Yi-Hsiu
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
RF noise shielding methods with different coverage areas (Pad and TML shielding) were implemented in two port test structures adopting 100-nm MOSFETs. Noise measurement reveals an effective suppression of NF(min) but increase of NF(50), simultaneously from the shielding methods. The suppression of NF(min) is contributed from the reduction of Re(Y(opt)) while the noise resistance R(n) is kept nearly the same. A lossy substrate model developed in our original work for a standard structure without shielding can be easily extended based on the layout and topology of the shielding schemes to predict the noise shielding effect and explain the mechanisms. The extended lossy substrate model indicates that the elimination of substrate loss represented by substrate RLC networks is the major mechanism contributing the reduction of NF(min). However, the increase of parasitic capacitance generated from the shielding structures is responsible for the degradation of f(T) and NF(50). The results provide an important insight and guideline for low noise RF circuit design.