Browsing by Author "Lin, Ying-Hsi"

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120% Harvesting Energy Improvement by Maximum Power Extracting Control for High Sustainability Magnetic Power Monitoring and Harvesting System
(2015-04-01)
Huang, Tzu-Chi
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Du, Ming-Jhe
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Kang, Yu-Chai
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Peng, Ruei-Hong
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Chen, Ke-Horng
The magnetic energy harvesting (MEH) circuit and the power monitoring system are proposed in this paper to enlarge the system sustainability on wireless sensing or the monitoring system. The proposed MEH circuit harvests magnetic power on power wires through a power sensing current transformer (CT) and charges power monitoring system. The MEH circuit includes the direct ac-dc rectifier and the maximum power extracting (MPE) control circuit. The direct ac-dc rectifier can directly rectify ac input to the dc output current. The proposed MPE control fits the characteristic of magnetic energy source compared to the conventional resistor emulation maximum power point tracking method. Owing to continuous tracking the maximum power of the CT, 120% harvesting power improvement can be achieved under the same CT\'s sensing current. Peak efficiency of 82% can be achieved under the sensing current of 8 A. The test chip is fabricated in 0.25 mu m CMOS process with an active area of 0.98 mm(2).
120V/ns Output Slew Rate Enhancement Technique and High Voltage Clamping Circuit in High Integrated Gate Driver for Power GaN FETs
(2015)
Yang, Hsiang-An
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Chiu, Chao-Chang
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Lai, Shin-Chi
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Chen, Jui-Lung
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Chang, Chih-Wei
High power density is a key point that power converters endeavor to pursue. However, it is rare that gate driver of power converter can switch under high supply voltage with a fast operation frequency. In this paper, a half-bridge driver with the slew rate enhancement (SRE) technique is proposed and its switching frequency can be increased to 25MHz under a 700V supply voltage. Besides, the proposed high voltage clamping circuit ensures all circuits operating in a safe region without any overvoltage problems in the bootstrap operation. With specifically developed high voltage high speed (HVHS) process, high-side and low-side circuits can be well shielded by the isolation well which is embedded in the level shifter device to minimize chip size.
200nA Low Quiescent Current Deep-Standby Mode in 28nm DC-DC Buck Converter for Active Implantable Medical Devices
(2015)
Chu, Li-Cheng
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Yang, Te-Fu
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Huang, Ru-Yu
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Su, Yi-Ping
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Lin, Chiun-He
the proposed deep-standby mode (DSM) is used in 28nm power management unit (PMU) for long-term usage in active implantable medical devices (AIMD). The PMU can upgrade its normal mode with the proposed embedded auto-cancellation (EAC) technique in order to have high accuracy even if the battery is aging and the PVT variations occur. The test chip fabricated in 28nm CMOS process features low quiescent current of 200nA and output voltage accuracy of 98%. Seamless transition among the DSM and the accurate mode demonstrates both low quiescent current and high accuracy can be achieved in the proposed PMU.
90% Peak Efficiency Single-Inductor-Multiple-Output DC-DC Buck Converter with Output Independent Gate Drive Control
(2015-01-01)
Su, Yi-Ping
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Lin, Chiun-He
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Peng, Shen-Yu
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Huang, Ru-Yu
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Yang, Te-Fu
93% Efficiency and 0.99 Power Factor in Pseudo-linear LED Driver
(2016-01-01)
Chiu, Shao-Wei
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Kuo, Chun-Chieh
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Chuang, Kai-Cheng
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Yang, Wen-Hau
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Chen, Ke-Horng
The proposed pseudo-linear LED driver can effectively solve the serious flicker in conventional linear LED driver (LLD). Besides, it has good electromagnetic interference (EMI) performance similar to that in conventional LLD at high AC input voltage. In the meanwhile, it has high power factor (PF) similar to boost switching regulator (SWR) LED driver at low AC input voltage. Furthermore, owing to the combination of line filter and the active full bridge rectifier, the pseudo-linear LED driver has a compact solution and high efficiency. The test chip was fabricated in 0.5 mu m 500V LDMOS process. Experimental results show 93% high efficiency, 6% total harmonic distortion (THD), and 0.99 PF at the power of 7W.
95% Light-load Efficiency Single-Inductor Dual-Output DC-DC Buck Converter with Synthesized Waveform Control Technique for USB Type-C
(2016)
Yang, Wen-Hau
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Lin, Chiun-He
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Chen, Ke-Horng
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Wey, Chin-Long
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Lin, Ying-Hsi
The proposed single-inductor dual-output (SIDO) converter can provide wide range in duty ratio control to convert input voltage 520V to dual output voltages 3.3V and 1.2V when its switching frequency is raised to 10MHz for compact size solution. The proposed synthesized waveform control (SWC) technique can emulate the inductor current without being affected by switching noise. Thus, the minimum allowable duty ratio can be lowered to 6% to meet the requirement of USB-C in one-stage low duty ratio conversion. Moreover, the switching frequency is dynamically decreased by the derived DC loading information from the SWC technique. Not only the output power MOSFET but also the main power MOSFET switch in a load-dependent switching frequency for power saving. 67% more power reduction can be obtained. 95% and 83% efficiency are achieved at light and heavy loads, respectively, when the silicon is limited within 1400 mu m*1350 mu m.
99% High Accuracy Knee Voltage Detection for Primary-side Control in Flyback Converter
(2015)
Tsai, Tsung-Hsun
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Chen, Ke-Horng
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Tsai, Tsung-Yen
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Lin, Jian-Ru
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Lin, Ying-Hsi
this paper proposed the adaptive knee voltage detection (KVD) technique to improve the output voltage accuracy of the primary side regulator. Owing to the insertion of the snubber circuit for reducing overshoot voltage, conventional KVD technique fails to get the output voltage information and thus to deteriorate the output voltage accuracy. Analysis of the snubber circuit and the resonance of the primary side can determine the band-pass filter in the proposed AKVD technique to get high accuracy output information without being affected by any kinds of resonances. Test chip designed in VIS 0.5 mu m BCD process demonstrates the accuracy of the output voltage higher than 99%. Besides, any abnormal detection won\'t happen and thus the output ripple can be kept low.
99.4% Peak Audio Signal Recovery Rate and Ultra-Low 0.32dB Matching Error with 10Hz High Resolution Filter Fitting Wearable Aided Speech Compensation System
(2015)
Lin, Yen-Ting
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Lai, Shin-Chi
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Chen, Shin-Hao
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Peng, Shen-Yu
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Chen, Ke-Horng
to get high sound quality, the proposed adaptive speech compensation (ASC) system fits psychoacoustic curves for individual needs. Moreover, characteristics of the speakers are considered by real-time speaker impedance estimation (RT-SIE) technique. Hence, original signal can be restored for every user with any speakers. ASC system has 99.4% peak original signal recovery rate by predicting and controlling output signal precisely. And the built-in 10Hz high resolution acoustic filter fitting scheme (AFFS) has less than 0.32dB matching error with an over 80dB hearing loss.
A 0.6 V Resistance-Locked Loop Embedded Digital Low Dropout Regulator in 40 nm CMOS With 80.5% Power Supply Rejection Improvement
(2015-01-01)
Chiu, Chao-Chang
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Huang, Po-Hsien
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Lin, Moris
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Chen, Ke-Horng
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Lin, Ying-Hsi
The proposed resistance-locked loop (RLL) can achieve high PSRR of -16 dB digital low dropout (DLDO) regulator without consuming much power which is the drawback in prior arts. Even at light loads, the RLL can be shut down for power saving. Furthermore, the duty compensator ensures DLDO stability under different duty ratio of supply voltage. The operation voltage of proposed DLDO can be down to 0.6 V and the peak current efficiency is 99.99%. The test chip was fabricated in 40 nm CMOS process with all the transistors implemented by core device for small silicon area.
A 2.5W Tablet Speaker Delivering 3.2W Pseudo High Power by Psychoacoustic Model Based Adaptive Power Management System
(2014)
Chen, Shin-Hao
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Peng, Shen-Yu
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Chen, Ke-Horng
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Lai, Shin-Chi
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Kang, Sheng
for a 2.5W speaker in tablets, the proposed adaptive power management (APM) system can deliver a pseudo high power of 3.2W with a +/- 4V supply because it suppresses 0.7W power on tones that may damage a 2.5W speaker and escape the notice of human ears. With z-domain digital signal processing (z-DSP) and psychoacoustic model, high efficient power management and high sound quality can be achieved simultaneously. Conventional automatic gain control (AGC) only has the ability of 0.32W power suppression. Moreover, suppressing power by conventional clipping technique increases total-harmonic-distortion (THD). In contrast, the proposed real-time dynamic loading impedance (RT-DLI) monitoring brings forward a way to solve the problem on speaker damage while keeping low THD during high sound pressure level (SPL). THD in the APM system is slightly higher than that of original sound 1.1dB, comparing to the disadvantage of 8.6dB increasing caused by conventional clipping technique.
A 20MHz Low Dropout Controlled Current Sensor for Constant On-Time Based Envelop Tacking Supply Modulator for Radio Frequency Power Amplifier
(2018-01-01)
Lin, Wei-Ting
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Lin, Zong-Yi
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Liu, Chia-Hao
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Chen, Ke-Horng
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Lin, Ying-Hsi
this paper presents a LDO-controlled current sensor for accelerating constant on-time (COT) switching regulators (SWRs) for high efficiency envelope tracking power modulators (ETSMs) for RF power amplifiers (RF PAs). The proposed LDO-controlled current sensor controls the feedback loop of the SWR, rather than the traditional current sensing technique, in the case of fast envelope tracking. The LDO regulator behaves as the master to rapidly trigger the SWR as a slave energy provider to rapidly deliver the average energy to the RF PA for high efficiency. The experimental results show that the test chip fabricated in 0.18 mu m CMOS process can accurately track the RF envelope signal, and the peak efficiency is 86.7% when the power is 0.95W.
A 20MS/s Buck/Boost Supply Modulator for Envelope Tracking Applications with Direct Digital Interface
(2014)
Yang, Shang-Hsien
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Wey, Chin-Long
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Chen, Ke-Horng
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Lin, Ying-Hsi
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Chen, Jing-Jia
a buck/boost supply modulator (BBSM) is proposed for 4G LTE RF power amplifier (RF-PA) envelope tracking applications. The H-bridges used in non-inverting buck/boost converters are metamorphosed into the current sources and switches of a 4-bit current-steering DAC-like supply modulator. Fast tracking speed is achieved through its inherent open-loop topology, while the direct digital interface provides easy control and integration with digital LTE baseband SoCs. The proposed BBSM is capable of delivering peak power of 2.8W at 20MS/s, with a peak efficiency of 75 %.
A 4.2 nW and 18 ppm/degrees C Temperature Coefficient Leakage-Based Square Root Compensation (LSRC) CMOS Voltage Reference
(2019-05-01)
Huang, Chao-Jen
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Lai, Yan-Jiun
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Yang, Yu-Jheng Ou
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Chen, Hung-Wei
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Kuo, Chun-Chieh
State-of-the-art CMOS-based voltage reference suffer from a trade-off between power dissipation and temperature coefficient (TC) due to the limited order of compensation in an advanced process which features a low supplied voltage (1 similar to 1.2 V). The proposed voltage reference with leakage-based square root compensation (LSRC) technique bias the substrate to offset TC with ultra-low leakage current (100 similar to 300 pA). On the other hand, the architecture provides an extensible order of compensation which is independent of voltage headroom. The two LSRC branches voltage reference implemented in 40 nm CMOS process achieves a within-wafer sigma/mu of 0.204 and a TC of 18 ppm/degrees C with a power consumption of 4.2 nW.
A 70W and 90% GaN-Based Class-E Wireless-Power-Transfer System with Automatic-Matching-Point-Search Control for Zero-Voltage Switching and Zero-Voltage-Derivative Switching
(2018-01-01)
Yeh, Che-Hao
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Lin, Yen-Ting
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Kuo, Chun-Chieh
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Huang, Chao-Jen
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Xie, Cheng-Yu
A 70W and 90% GaN-Based Class-E Wireless-Power-Transfer System with Automatic-Matching-Point-Search Control for Zero-Voltage Switching and Zero-Voltage-Derivative Switching
(2018-01-01)
Yeh, Che-Hao
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Lin, Yen-Ting
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Kuo, Chun-Chieh
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Huang, Chao-Jen
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Xie, Cheng-Yu
A 96%-Efficiency and 0.5%-Current-CrossRegulation Single-Inductor Multiple Floating-Output LED Driver with 24b Color Resolution
(2016)
Yang, Hsiang-An
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Yang, Wen-Hau
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Chen, Ke-Horng
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Wey, Chin-Long
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Lin, Ying-Hsi
A 97% Maximum Efficiency Fully Automated Control Turbo Boost Topology for Battery Chargers
(2019-11-01)
Muniandi, Balakumar
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Huang, Chao-Jen
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Kuo, Chun-Chieh
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Yang, Te-Fu
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Chen, Ke-Horng
In this paper, the proposed topology of a fully automated control (FAC) battery charger that provides turbo-boost operation and fully automated detection without any feedback from the system is discussed. It uses closed-loop control for automatic system load detection and automatically adjusts the battery discharge current. The advantages include shortened battery discharge time and maximum power provided by the adapter. Therefore, the FAC technique is flexible for any load system that is limited to battery chargers with the turbo boost mode support. In addition, to avoid over discharge, a battery protection circuitry is also included. The test chip is fabricated using a 0.25- $\mu \text{m}$ CMOS process, with a maximum efficiency of 94.58 & x0025; when the charger operates in the turbo boost mode, and achieves 97 & x0025; maximum efficiency when the charger operates in buck charge mode.
A 99.2% Tracking Accuracy Single-Inductor Quadruple-Input-Quadruple-Output Buck-Boost Converter Topology with Periodical Interval Perturbation and Observation MPPT
(2018-01-01)
Huang, Chao-Jen
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Ma, Yao-Sheng
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Yang, Wen-Hau
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Lin, Yen-Ting
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Kuo, Chun-Chieh
this paper provides a Single-Inductor Quadruple-Input--Quadruple-Output buck-boost converter to achieve maximum tracking efficiency of 99,2% due to continuous supply in one cycle. The Maximum Power Point (MPP) tracking mode and the Harvest Energy Delivering (RED) mode harvest each energy harvesting source, deliver energy to the battery and supply it to the loading system in one cycle. Each output voltage ranges from 600mV to 2.5V and the maximum output power is up to 60mW. The peak efficiency is 91.2%.
A Battery-Free 217 nW Static Control Power Buck Converter for Wireless RF Energy Harvesting With alpha-Calibrated Dynamic On/Off Time and Adaptive Phase Lead Control
(2012-04-01)
Huang, Tzu-Chi
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Hsieh, Chun-Yu
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Yang, Yao-Yi
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Lee, Yu-Huei
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Kang, Yu-Chai
Abattery-free nano-power buck converter with a proposed dynamic on/off time (DOOT) control can achieve high conversion efficiency over a wide load range. The DOOT control can predict the on/off time at different input voltages without a power consuming zero current detection (ZCD) circuit, as well as suppress static power in idle periods. To adapt to the fluctuations in a harvesting system, the proposed alpha-calibration scheme guarantees accurate ZCD over process, voltage variation, and temperature (PVT) in the DOOT to improve power conversion efficiency. Furthermore, the adaptive phase lead (APL) mechanism can improve inherent propagation delay attributable to low-power and non-ideal comparator, thus improving load regulation by a maximum of 30 mV. The test chip was implemented in 0.25-mu m CMOS process with a die area of 0.39 mm(2). Experimental results showed 95% peak efficiency, low static power of 217 nW and good load regulation of 0.1 mV/mA, which are suitable for RF energy harvesting applications.
A Buck Power Factor Correction Converter with Predictive Quadratic Sinusoidal Current Modulation and Line Voltage Reconstruction
(2016-09)
Yang, Shang-Hsien
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Meng, Che-Hao
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Chiu, Chao-Chang
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Chang, Chih-Wei
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Chen, Ke-Horng
A buck power factor correction (PFC) converter operating in continuous conduction mode (CCM) is influenced by the dead zone, which introduces distortion related to the input line voltage. Such phenomenon limits the maximum power factor (PF) and the minimum total harmonic distortion (THD) achievable. By deriving a methodology to achieve predictive line voltage reconstruction (PLVR), the influence of the dead zone is mitigated. With the prediction of quadratic sinusoidal current modulation ((PSCM)-C-2), the line current is shaped into sinusoid waveform that is in-phase with input line voltage, crucial for. Consequently, the proposed CCM buck PFC can achieve high PF, low THD, and efficiency simultaneously. A test chip was fabricated in 0.5-mu m Bipolar-CMOS-DMOS (BCD) process. The experimental results show a peak PF of 0.95 and a peak efficiency of 98% at 110 Vac.