Browsing by Author "Lin, Yu-Tzung"
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Item type:Item, Architecture implementation of class-D amplifiers using digital-controlled multiphase-interleaved PWM technique(2006) ;Lin, Yu-Tzung ;Lee, Chi-Yang ;Tzou, Ying-Yu ;電控工程研究所Institute of Electrical and Control EngineeringThe class-D amplifier has the advantages of having a high efficiency, a small-size and gains its wide applications in battery-powered audio systems. However, its output power is limited by the rating of its output transistors. This paper presents the development of a new architecture for the realization of a class-D audio amplifier using a digital-controlled multi-phase interleaved PWM converter to enhance its output power. This interleaved technique is widely used in DC-DC converters. A digital current control technique with interleaved PWM generation was developed to reduce the total harmonic distortion (THD) of the output current under lower PWM switching frequency. A comparative evaluation of a single-phase and a three-phase class-D amplifier structure is presented. Furthermore, the design and implementation of a digital control IC, including an ADC synchronous sampler, a digital compensator, and a phase-shift PWM generator, is introduced. Computer simulations and experimental verifications are given to illustrate the feasibility and performance of the proposed technique.Item type:Item, Development of a Mixed-Signal PFC Control IC with Fast Dynamic Response(2009) ;Chan, Ming-Hau ;Lin, Yu-Tzung ;Tzou, Ying-Yu ;電控工程研究所Institute of Electrical and Control EngineeringThis paper presents a mixed-signal power-factor-correction (PFC) control IC for the single-phase critical-conduction-mode (CRM) boost AC/DC converters. The peak current mode control is used and realized by using the analog circuit technique. The outer voltage loop control adopts digital control technique to implement. This paper analyzes effect of the hysteresis band of the comparator in current loop is implemented by analog circuit. In digital voltage loop, this paper proposes usage of a digital notch filter to achieve fast dynamic response under large step load variations while maintaining a low total-harmonic-distortion (THD) and a high power factor (PF). The proposed mixed-signal PFC control scheme has been verified by using computer simulation via PSIM and Simplis to validate feasibility.Item type:Item, Digital control of a multi-phase interleaved PWM inverter with minimal total harmonic distortion(2007) ;Lin, Yu-Tzung ;Tzou, Ying-Yu ;電控工程研究所Institute of Electrical and Control EngineeringThis paper presents a digital repetitive control scheme for the minimization of output voltage total harmonic distortion (THD) of a PWM inverter under large unknown nonlinear load. The multi-phase interleaved PWM inverter has been adopted to enhance the effective switching frequency as well as to share the load current. The realization of a digital control for PWM inverter, such as sampling delay and quantization error, may introduce many nonlinear effects to distort its output waveforms. A systematic design procedure is developed to minimize selected range of harmonic spectrum by shaping the output impedance by so that its output voltage THD can be lower than a specified value with given design constraints. The proposed control scheme has been realized with fully digital design by using a single-chip FPGA implementation and verified by using co-simulation technique via a VHDL simulator Modelsim combined with a system-level block diagram oriented simulator Simulink.Item type:Item, Digital Control of Boost PFC AC/DC Converters with Low THD and Fast Dynamic Response(2009) ;Lin, Yu-Tzung ;Tzou, Yinu-Yu ;電控工程研究所Institute of Electrical and Control EngineeringThis paper presents a digital control scheme for boost power-factor-correction (PFC) AC/DC converters to achieve both low total-harmonic-distortion (THD) and fast dynamic response under large load variations. Compared with conventional control methods, the proposed digital control scheme can achieve a lower THD by sensing the input line voltage for feed-forward compensation in current loop to eliminate disturbance coming from the input line voltage, this paper also proposes the off-time duty ratio control to reduce the input current distortion. A synchronous sampling technique based on the double-line frequency can improve the dynamic response of the output voltage. The proposed control scheme has been verified by using simulation software PSIM and realized by using a DSP TMS3202812 in applications to a 1400 W prototype of boost PFC AC/DC converter. Experimental results are given to illustrate the feasibility of the proposed control scheme.Item type:Item, Digital Primary-Side Sensing Control for Flyback Converters(2009) ;Chang, Che-Wei ;Lin, Yu-Tzung ;Tzou, Ying-Yu ;電機工程學系Department of Electrical and Computer EngineeringPrimary-side sensing (PSS) technique can be used for the output voltage or current regulation by employing an auxiliary winding. However, the sensed voltage may be corrupted by switching noise due to leakage inductance, winding resistance, and nonlinearity of the magnetic core, therefore the sensed voltage can only achieve limited accuracy. With the advance of power control IC realization technology, more complicated control and estimation algorithms can be realized by using analog, digital, or mixed-signal technologies. This paper introduces a digital control method to make the influence of nonideal factors as low as possible. A key factor for accurate voltage sensing is the determination of sampling instant on the auxiliary winding. A prototype of a DCM DC/DC flyback converter with digital signal processor has been realized to verify the proposed digital PSS scheme.Item type:Item, Load Adaptive Control for Mixed-Signal PFC Control IC(2009) ;Chan, Ming-Hau ;Lin, Yu-Tzung ;Tzou, Ying-Yu ;電控工程研究所Institute of Electrical and Control EngineeringThis paper presents a mixed-signal power-factor-correction (PFC) control IC for the single-phase critical-conduction-mode (CRM) boost AC/DC converters. The peak current mode control is applied and analyzed by using the analog circuit. The voltage control loop is implemented in digital approach. This paper analyzes effect of the hysteresis band effect of the analog current comparator in current loop. In digital voltage loop, the proper quantization resolutions both ADC and DAC are determined. The digital voltage controller uses a digital notch filter to achieve fast dynamic response and a low total-harmonic-distortion (THD) with high power factor (PF). A load adaptive control scheme to maintain same dynamic response of the output voltage at different load conditions change. The proposed mixed-signal PFC control scheme has been verified by using computer simulation with experimental results to validate feasibility.Item type:Item, Single-chip FPGA implementation of a digital VRM controller with interlaced sampling and control technique(2007) ;Lin, Yu-Tzung ;Wang, Yi-Chung ;Tzou, Ying-Yu ;電控工程研究所Institute of Electrical and Control EngineeringThis paper presents the design and implementation of a singe-chip FPGA based digital VRM controller for multi-phase synchronous buck converters with interlaced current sampling and load current feed-forward compensation techniques. The sampling of the inductor current is synchronized with the middles of leading and trailing edges of the PWM signal of each synchronous buck converter for both turn-on and turn-off. The proposed sampling scheme has a high noise immunity to the common-mode switching noises induced by the switching of the MOSFET and its parasitic junction capacitances resulted by the heat sink. A true average current signal with minimum response time can be measured with accuracy within a switching period. The timing clocks for the digital controller and the digital PWM generator are interlaced with each other to achieve a minimum delay at a same sampling and switching frequency. A digital interface is designed for the connected microprocessor load to adjust the output voltage and provide feed-forward load current compensation according to its clock rate, loading factor, and pipeline scheduling. The realization scheme for the proposed digital VRM controller has been described. Simulation analysis and experimental verifications are given to illustrate the fast dynamic response control of VRM for advanced microprocessors.