Browsing by Author "Lin, Yueh-Chin"

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A 60-nm-thick enhancement mode In0.65Ga0.35As/InAs/In0.65Ga0.35As high-electron-mobility transistor fabricated using Au/Pt/Ti non-annealed ohmic technology for low-power logic applications
(2016-02)
Fatah, Faiz Aizad
;
Lin, Yueh-Chin
;
Liu, Ren-Xuan
;
Yang, Kai-Chun
;
Lin, Tai-We
A 60-nm-thick E-mode In0.65Ga0.35As/InAs/In0.65Ga0.35As high-electron-mobility transistor (HEMT) was successfully fabricated and evaluated by using Au/Pt/Ti-based non-annealed ohmic technology for high-speed and low-power logic applications. The device exhibited a minimal SS of 69mV/decade, a lower DIBL of 30mV/V, an ION/IOFF ratio above 1.2 x 10(4) at V-DS = 0.5V and a high f(T) of 378GHz and f(max) of 214GHz at V-DS = 1.0V. These results demonstrate that non-annealed ohmic contacts can be used for fabricating E-mode In0.65Ga0.35As/InAs/In0.65Ga0.35As HEMTs with excellent electrical characteristics. The fabricated HEMTs are likely to find use in future high-speed and low-power logic applications. (C) 2016 The Japan Society of Applied Physics.
A Cu-Metallized InGaP/GaAs Heterojunction Bipolar Transistor with Reliable Pd/Ge/Cu Ohmic Contact for Power Applications
(2010)
Huang, Jui-Chien
;
Lin, Yueh-Chin
;
Tseng, Yu-Ling
;
Chen, Ke-Shian
;
Lu, Po-Chin
A Cu-metallized InGaP/GaAs heterojunction bipolar transistor (HBT) using a Pd/Ge/Cu n-type ohmic contact, a Pt/Ti/Pt/Cu p-type ohmic contact, and a Ti/Pt/Cu interconnect has been fabricated for power applications. The 4 x 20 mu m(2) HBT had an output power of 11.25 dBm with a power-added efficiency of 35.1%. After applying current-accelerated stress for 24 h, the current gain remained larger than 125. The device was also annealed at 200 degrees C for 24 h, and showed a slight decrease in output power from 10.06 to 9.83 dBm. The results demonstrated that reliable Cu metallization can be used for fabricating InGaP/GaAs HBTs for power applications. (C) 2010 The Japan Society of Applied Physics
A delta-doped InGaP/InGaAs pHEMT with different doping profiles for device-linearity improvement
(2007-07-01)
Lin, Yueh-Chin
;
Chang, Edward Yi
;
Yamaguchi, Hiroshi
;
Wu, Wei-Cheng
;
Chang, Chun-Yen
In this paper, delta-doped InGaP/InGaAs pseudomorphic high-electron-mobility transistors (pHEMTs) with doping-profile modifications are investigated in order to improve the device linearity. The proposed modification was based on the third-order intermodulation distortion (IM3) and the third-order intercept point (IP3) analysis using a simple equivalent circuit of the devices. The correlations of the extrinsic transconductance (Gm) with IM3 and IP3 indicate that the flatness of Gin, as a function of gate-bias causes a lower IM3 level. On the other hand, a high Gm with a flatter Gm distribution results in higher IP3 value for the device. Therefore, doping modifications that improve the flatness of the Gm distribution will also improve the device linearity. Doping modifications in the Schottky layer (Schottky layer doped) and in the channel layer (channel doped) of the conventional delta-doped InGaP/InGaAs pHEMT were investigated. It was also found that extra doping, either in the channel region or in the Schottky layer, improved the flatness of the Gm distribution under different gate-bias conditions. This achieved a lower IM3 and a higher IP3 with a small sacrifice in the peak Gm value. The power performances of these devices were tested at different drain biases. Even though it had the lowest electron mobility among the three different types of devices studied, the channel-doped device demonstrated the best overall linearity performance, the highest IP3 value, the lowest IM3 level, and the best adjacent-channel power ratio under code-division multiple-access modulation.
A simple extraction method for parasitic series resistances in GaN HEMTs considering non-quasi-static effects
(2019-05-01)
Nagarajan, Venkatesan
;
Chen, Kun-Ming
;
Wang, Huan-Chung
;
Singh, Sankalp Kumar
;
Anandan, Deepak
A simple technique for extracting the bias-dependent parasitic series resistances of the GaN-based high electron mobility transistor (HEMT) is demonstrated in this paper. With considering the non-quasi-static effect in devices, new analytical Z-parameter formulations are derived to determine parasitic resistances using the curve-fitting algorithm. More accuracy parasitic resistances can be obtained over a wide fitting frequency range compared to the conventional method which ignores the non-quasi-static effect. Here the intrinsic parameters are then calculated directly from intrinsic Y-parameters after de-embedding the parasitic elements in the small-signal equivalent circuit. An excellent agreement between the measured and simulated S-parameters from 100 MHz to 40 GHz is achieved, which validates the feasibility of our method for extracting the bias-dependent parasitic resistances.
AlGaAs/InGaAs high electron mobility transistor grown on Si substrate with Ge/Ge(x)Si(1-x) metamorphic buffer layers
(2008-09-01)
Chang, Edward Yi
;
Huang, Jui-Chien
;
Lin, Yueh-Chin
;
Hsieh, Yen-Chang
;
Chang, Chia-Yuan
Al(0.12)Ga(0.88)As/In(0.18)Ga(0.82)As high-electron-mobility transistor (HEMT) growth oil a Si substrate using the Ge/Ge(x)Si(1-x) buffer is demonstrated. This is the first demonstration of Al(0.12)Ga(0.88)As/In(0.18)Ga(0.82)As HEMT growth on a Ge/Ge(x)Si(1-x) metamorphic buffer layer. The electron mobility ill tile In(0.18)Ga(0.82)As channel of the HEMT sample was 3.550cm(2)/(Vs). After fabrication. the HEMT device demonstrated a saturation current of 150mA/mm with a transconductance 01 155mS/ inns. The wel behaved characteristics of the HEMT device oil the Si substrate are believed to be due to the very thin buffer layer achieved and the lack of tile antiphase boundary (APB) formation and Ge diffusion into the GaAs layers.
AlGaAs/InGaAs high electron mobility transistor grown on Si substrate with Ge/GexSi1-x metamorphic buffer layers
(2008-09-01)
Chang, Edward Yi
;
Huang, Jui-Chien
;
Lin, Yueh-Chin
;
Hsieh, Yen-Chang
;
Chang, Chia-Yuan
Al0.12Ga0.88As/In0.18Ga0.82As high-electron-mobility transistor (HEMT) growth oil a Si substrate using the Ge/GexSi1-x buffer is demonstrated. This is the first demonstration of Al0.12Ga0.88As/In0.18Ga0.82As HEMT growth on a Ge/GexSi1-x metamorphic buffer layer. The electron mobility ill tile In0.18Ga0.82As channel of the HEMT sample was 3.550cm(2)/(Vs). After fabrication. the HEMT device demonstrated a saturation current of 150mA/mm with a transconductance 01 155mS/ inns. The wel behaved characteristics of the HEMT device oil the Si substrate are believed to be due to the very thin buffer layer achieved and the lack of tile antiphase boundary (APB) formation and Ge diffusion into the GaAs layers.
AlGaN/GaN MIS-HEMTs With High Quality ALD-Al2O3 Gate Dielectric Using Water and Remote Oxygen Plasma As Oxidants
(2018-12-01)
Wang, Huan-Chung
;
Hsieh, Ting-En
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Lin, Yueh-Chin
;
Luc, Quang Ho
;
Liu, Shih-Chien
We demonstrate the electrical performances of AlGaN/GaN metal-insulator-semiconductor-high electron mobility transistors (MIS-HEMTs) with high quality Al2O3 gate dielectric deposited by plasma enhanced atomic layer deposition using both H2O and remote O-2 plasma as oxygen sources. Excellent gate-dielectric/GaN interface and Al2O3 film quality were obtained, resulting in a very small threshold voltage hysteresis and a low interface trap density. The MIS-HEMT device exhibited high on/off current ratio of similar to 10(10), steep subthreshold slope, small gate leakage current, low dynamic on-resistance degradation, and effectively current collapse suppression. These results indicate that incorporating remote O-2 plasma in the ALD-Al2O3 deposition process is an effective and simple way to provide high quality gate dielectric for the GaN MIS-HEMTs production.
An Al(2)O(3) AlGaAs/InGaAs Metal-Oxide-Semiconductor PHEMT SPDT Switch with Low Control Currents for Wireless Communication Applications
(2010-01-01)
Wu, Yun-Chi
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Lin, Yueh-Chin
;
Chang, Edward Yi
;
Lee, C. T.
;
Kei, Chi-Chung
An AlGaAs/InGaAs metal-oxide-semiconductor pseudomorphic high electron mobility transistor (MOS-PHEMT) single- pole-double-throw (SPDT) switch using Al(2)O(3) high-k gate dielectric by atomic layer deposition is fabricated. The MOS-PHEMT exhibited a comparable dc performance and a much lower gate current compared to PHEMT. Radio-frequency (rf) test shows that the MOS-PHEMT switch has an insertion loss of less than 0.5 dB, an isolation larger than 30 dB, a return loss larger than 15 dB, and an input power for 1 dB compression of 31.4 dBm at 2.5 GHz. Overall, MOS-PHEMT monolithic microwave integrated circuits switches have comparable rf performance to PHEMT switches but with much lower dc power consumption. (C) 2010 The Electrochemical Society. [DOI: 10.1149/1.3380967] All rights reserved.
An Al2O3 AlGaAs/InGaAs Metal-Oxide-Semiconductor PHEMT SPDT Switch with Low Control Currents for Wireless Communication Applications
(2010-01-01)
Wu, Yun-Chi
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Lin, Yueh-Chin
;
Chang, Edward Yi
;
Lee, C. T.
;
Kei, Chi-Chung
An AlGaAs/InGaAs metal-oxide-semiconductor pseudomorphic high electron mobility transistor (MOS-PHEMT) single- pole-double-throw (SPDT) switch using Al2O3 high-k gate dielectric by atomic layer deposition is fabricated. The MOS-PHEMT exhibited a comparable dc performance and a much lower gate current compared to PHEMT. Radio-frequency (rf) test shows that the MOS-PHEMT switch has an insertion loss of less than 0.5 dB, an isolation larger than 30 dB, a return loss larger than 15 dB, and an input power for 1 dB compression of 31.4 dBm at 2.5 GHz. Overall, MOS-PHEMT monolithic microwave integrated circuits switches have comparable rf performance to PHEMT switches but with much lower dc power consumption. (C) 2010 The Electrochemical Society. [DOI: 10.1149/1.3380967] All rights reserved.
An AlGaAs/InGaAs HEMT Grown on Si Substrate with Ge/GexSi1-x Metamorphic Buffer Layers
(2008)
Chang, Edward Yi
;
Lin, Yueh-Chin
;
Hsiao, Yu-Lin
;
Hsieh, Y. C.
;
Chang, Chia-Yuan
An AlGaAs/InGaAs HEMT grown on Si substrate with Ge/GexSi1-x buffer is demonstrated. The Ge/GexSi1-x metamorphic buffer layer used in this structure was only 1.0 mu m thick. The electron mobility in the In0.18Ga0.82As channel of the HEMT sample was 3,550 cm(2)/Vs. After fabrication, the HEMT device demonstrated a saturation current of 150 mA/mm and a maximum transconductance of 155 mS/mm. The well behaved characteristics of the HEMT device on the Si substrate are believed to be due to the very thin buffer layer achieved and the lack of the antiphase boundaries (APBs) formation and Ge diffusion into the GaAs layers. Index Terms: HEW GaAs on Si, SiGe buffer layer
An Au-free GaN High Electron Mobility Transistor with Ti/Al/W Ohmic Metal Structure
(2015)
Yao, Jing-Neng
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Lin, Yueh-Chin
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Chuang, Yu-Lin
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Huang, Yu-Xiang
;
Shih, Wang-Cheng
We demonstrate the Au-free GaN HEMT device with the Ti/Al/W Ohmic metal structure. Excellent surface roughness 4.88nm for Ti/Al/W Ohmic stucture was achieved after metallization. The DC characteristics is comparable with conventional HEMTs and the stress performance with high voltage is better than conventional HEMTs.
Au-Free GaN High-Electron-Mobility Transistor with Ti/Al/W Ohmic and WN (X) Schottky Metal Structures for High-Power Applications
(2016-07)
Hsieh, Ting-En
;
Lin, Yueh-Chin
;
Chu, Chung-Ming
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Chuang, Yu-Lin
;
Huang, Yu-Xiang
In this study, an Au-free AlGaN/GaN high-electron-mobility transistor (HEMT) with Ti/Al/W ohmic and WNx Schottky metal structures is fabricated and characterized. The device exhibits smooth surface morphology after metallization and shows excellent direct-current (DC) characteristics. The device also demonstrates better performance than the conventional HEMTs under high voltage stress. Furthermore, the Au-free AlGaN/GaN HEMT shows stable device performance after annealing at 400A degrees C. Thus, the Ti/Al/W ohmic and WN (X) Schottky metals can be applied in the manufacturing of GaN HEMT to replace the Au based contacts to reduce the manufacturing costs of the GaN HEMT devices with comparable device performance.
BUFFER-OPTIMIZED IMPROVEMENT IN RF LOSS OF ALGAN/GAN HEMTS ON 4-INCH SILICON (111)
(2017-01-01)
Luong, Tien Tung
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Lumbantoruan, Franky
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Chen, Yen-Yu
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Ho, Yen-Teng
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Lin, Yueh-Chin
The effect of different buffer layers on the RF losses of GaN-based high-mobility-transistors (HEMTs) on Si substrate has been studied. It is found that the electron inversion layer induced by the residual tensile stress in AlN buffer is responsible for a dominant loss factor. It is first time such mechanisms of the RF loss of GaN/Si is discussed. It is proven that using a thin high-low-high temperature (HLH) AlN buffer reducing the tensile stress in AlN consequently reduces the RF loss.
Communication-Potential of the pi-Gate InAs HEMTs for High-Speed and Low-Power Logic Applications
(2019-06-07)
Yao, Jing-Neng
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Lin, Yueh-Chin
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Wong, Ying-Chieh
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Huang, Ting-Jui
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Hsu, Heng-Tung
Composite channel (In0.65Ga0.35As/InAs/In0.65Ga0.35As) high electron mobility transistors (HEMTs) with pi-gate structure were investigated for high-speed and low-power logic applications. The conventional and tri-gate MESA HEMTs were compared with the pi-gate device for evaluation. The pi-gate device exhibited the best maximum transconductance value of 1584 mS/mm, on-state current of 332mA/mm, subthreshold swing (SS) of 78.1 mV/decade, and I-ON/I-OFF ratio of 3 x 10(4) at V-DS = 0.5 V at room temperature. These results indicated that the designed pi-gate InAs devices improve the electrical characteristics of InAs HEMTs for high-speed and low-power logic applications. (c) 2019 The Electrochemical Society.
Demonstrating 1 nm-oxide-equivalent-thickness HfO2/InSb structure with unpinning Fermi level and low gate leakage current density
(2013-09-30)
Hai-Dang Trinh
;
Lin, Yueh-Chin
;
Minh-Thuy Nguyen
;
Hong-Quan Nguyen
;
Quoc-Van Duong
In this work, the band alignment, interface, and electrical characteristics of HfO2/InSb metaloxide-semiconductor structure have been investigated. By using x-ray photoelectron spectroscopy analysis, the conduction band offset of 1.78 +/- 0.1 eV and valence band offset of 3.35 +/- 0.1 eV have been extracted. The transmission electron microscopy analysis has shown that HfO2 layer would be a good diffusion barrier for InSb. As a result, 1 nm equivalent-oxide-thickness in the 4 nm HfO2/InSb structure has been demonstrated with unpinning Fermi level and low leakage current of 10(-4) A/cm(-2). The D-it value of smaller than 10(12) eV(-1) cm(-2) has been obtained using conduction method. (C) 2013 AIP Publishing LLC.
Demonstrating 1 nm-oxide-equivalent-thickness La2O3 and HfO2 multi-layer composite oxides on In0.53Ga0.47As MOS capacitor
(2016-01-08)
Wu, Wen-Hao
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Lin, Yueh-Chin
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Hou, Tzu-Ching
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Lin, Tai-Wei
;
Hsu, Hisang-Hua
The use of a high k composite dielectric composed of La2O3 and HfO2 layers as the gate dielectric for In0.53Ga0.47As MOS application is proposed. Two multi-layer structures of La2O3 (1 nm)/HfO2 (1 nm) and La2O3 (0.5 nm)/HfO2 (0.5 nm) were deposited and annealed at 450 and 500 degrees C for device performance comparison. X-ray photoelectron spectroscopy, TEM and C-V measurements were used for the interface analysis between the oxide and the semiconductor. Finally, a 1 nm equivalent-oxide-thickness dielectric with small hysteresis of 88 mV and D-it of 1.9 x 10(12) cm(-2) eV(-1) was achieved for six layers of an La2O3 (0.5 nm)/HfO2 (0.5 nm) composite oxide structure on an In0.53Ga0.47As MOS capacitor with a post-deposition annealing temperature of 450 degrees C.
Design, Fabrication, and Reliability of Low-Cost Flip-Chip-On-Board Package for Commercial Applications up to 50 GHz
(2012-03-01)
Hsu, Li-Han
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Oh, Chee-Way
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Wu, Wei-Cheng
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Chang, Edward Yi
;
Zirath, Herbert
This paper presents a flip-chip-on-board (FCOB) packaging technology using a Rogers RO3210 laminate for microwave applications. Compared to the conventional microwave packaging architecture, the proposed FCOB technology skips one level of the ceramic package and thus results in lower reflections and manufacturing costs. To fulfill the small dimension requirement on printed circuit boards, the coplanar waveguide (CPW) transmission line and flip-chip bump were fabricated on a high-k RO3210 board (epsilon(r) = 10.2) with photolithography and electroplating. The GaAs chip patterned with the CPW line was then flip-chip-mounted onto the RO3210 laminate board. This structure displayed excellent performance from dc to 50 GHz with a return loss S-11 greater than 18 dB and insertion loss S-21 less than 0.5 dB. Meanwhile, the flip-chip bonding of the in-house-fabricated In0.52Al0.As-48/In0.6Ga0.4As metamorphic high-electron-mobility transistor devices on RO3210 also displayed excellent gain performance with a small degradation of 1 dB from dc to 40 GHz, showing the potential of implementing microwave integrated circuits on RO3210. To enhance the mechanical reliability, an epoxy-based underfill was injected into the flip-chip assemblies. Thermal cycling tests were performed to test the interconnect reliability, and the results indicated that the samples passed the thermal cycling test at least up to 600 cycles, showing excellent reliability for commercial applications. To the best of the authors' knowledge, this is the first study that evaluates the use of the RO3210 laminate for microwave flip-chip in open literature.
Device Simulation of P-InAlN-Gate AlGaN/GaN High Electron Mobility Transistor
(2014-01-01)
Shrestha, Niraj Man
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Lin, Yueh-Chin
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Chang, Han-Tung
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Li, Yiming
;
Chang, Edward Yi
Enhancement mode AlGaN/GaN high electron mobility transistor with p-InAlN gate is designed and successfully studied its electrical properties. Threshold voltage of the device is 1.9 V, which is required magnitude of threshold voltage for real device. Similarly, the maximum drain current is 520 mA/mm and trasconductance is 183 mS/mm, which is the record estimation for enhancement-mode (e-mode) device with recorded threshold voltage. P-InAlN layer injects hole to the barrier at higher gate voltage and results in comparatively larger drain current. Selective area etching and re-grow AlInN causes thin barrier layer beneath the gate. This recess like p-InAlN structure can reduce the concentration of 2DEG; and thus results the high magnitude of threshold voltage.
Dislocation reduction in GaN film using Ga-lean GaN buffer layer and migration enhanced epitaxy
(2011-07-29)
Wong, Yuen-Yee
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Chang, Edward Yi
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Wu, Yue-Han
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Hudait, Mantu K.
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Yang, Tsung-Hsi
A GaN buffer layer grown under Ga-lean conditions by plasma-assisted molecular beam epitaxy (PAMBE) was used to reduce the dislocation density in a GaN film grown on a sapphire substrate. The Ga-lean buffer, with inclined trench walls on its surface, provided an effective way to bend the propagation direction of dislocations, and it reduced the dislocation density through recombination and annihilation processes. As a result, the edge dislocation density in the GaN film was reduced by approximately two orders of magnitude to 2 x 10(8) cm(-2). The rough surface of the Ga-lean buffer was recovered using migration enhanced epitaxy (MEE), a process of alternating deposition cycle of Ga atoms and N(2) radicals, during the PAMBE growth. By combining these two methods, a GaN film with high-crystalline-quality and atomically-flat surface can be achieved by PAMBE on a lattice mismatch substrate. (C) 2011 Elsevier B.V. All rights reserved.
Effect of annealing processes on the electrical properties of the atomic layer deposition Al2O3/In0.53Ga0.47As metal oxide semiconductor capacitors
(2014-04-01)
Quang-Ho Luc
;
Chang, Edward Yi
;
Trinh, Hai-Dang
;
Hong-Quan Nguyen
;
Binh-Tinh Tran
The influence of different annealing processes including post deposition annealing (PDA) and post metallization annealing (PMA) with various temperatures (250-400 degrees C) and ambient [N-2 and forming gas (FG)] on the electrical characteristics of Pt/Al2O3/In0.53Ga0.47As MOSCAPs are systemically studied. Comparing to samples underwent high PDA temperature, the higher leakage current has been observed for all of samples underwent high PMA temperature. This has resulted in the degradation of capacitance-voltage (C-V) behaviors. In conjunction with the current-voltage (J-V) measurement, depth profiling Auger electron spectroscopy (AES) and high-resolution transmission electron microscopy (HRTEM) analyses evidence that the out-diffusion of metal into oxide layer is the main source of leakage current. The noticeable passivation effect on the Al2O3/InGaAs interface has also been confirmed by the samples that underwent PDA process. (C) 2014 The Japan Society of Applied Physics