Browsing by Author "Lin, Yuwen (Dave)"

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Fast-yet-accurate Variation-Aware Current and Voltage Modelling of Radiation-Induced Transient Fault
(2016)
Huang, Hsuan-Ming (Ryan)
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Lin, Yuwen (Dave)
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Wen, Charles H. -P.
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電機學院
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College of Electrical and Computer Engineering
For robust systems, it is important to mitigate radiation effect in early stages to reduce the design cost. Traditionally, a double-exponential current source is widely used to model the transient fault for analyzing the radiation effects. However, in light of complicating effects in the advanced technologies, such approach is no longer sufficient to estimate transient faults and may lead to inaccurate results. Therefore, we propose a fast-yet-accurate approach to model the radiation-induced transient fault, meanwhile considering the interaction between its transient current and transient voltage. Experimental results show that the proposed method can achieve 105 X speedup with an average accuracy loss of only 2.6% compared to the 3D mixed-mode TCAD simulation. Moreover, variation sources also become big issues with the progressing technology nodes and thus the proposed method is then extended to incorporate these variations during transient-fault analysis. As a result, sensitivity analysis that covers voltage, gate-length and device-width variations can be performed fast and accurately in our method.
Radiation-Hardened Designs for Soft-Error-Rate Reduction by Delay-Adjustable D-Flip-Flops
(2017-01-01)
Lin, Yuwen (Dave)
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Wen, Charles H-P
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Chiueh, Herming
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電機工程學系
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Department of Electrical and Computer Engineering
For reducing soft error rate (SER) in system-level failures, this paper proposes a radiation-hardened design by Delay Adjustable D Flip-Flop (DAD-FF), which can be generally applied to sequential circuits such as shift registers. DAD-FF, modified from the Built-In Soft-Error Resilience (BISER) latch, can be easily integrated in the CAD flow and its delay can be adjusted to reject particle strikes with the maximum energy level. As a result, at the device level, DAD-FF eliminates 99.999997%(1) soft errors by heavy ions on a satellite orbiting at a height of 720 km, and shows greater reduction on SER (e.g. 1.3 x 10(10)X in the best case) than the standard DFF (STD-FF) through TCAD and SPICE simulation. Moreover, a real chip was also fabricated in a CMOS 90nm technology and performed the experiment of radiation exposure in UCL, Belgium. The laboratory measurement indicates that at the system level, the radiation-hardened design by DAD-FFs achieves 15.69X and 2.62X improvements on the overall SER, compared with those by STD-FFs and DICEs, respectively.