Browsing by Author "Lin, Zer-Ming"

Now showing 1 - 11 of 11

A New Methodology for Probing the Electrical Properties of Heavily Phosphorous-Doped Polycrystalline Silicon Nanowires
(2013-04-01)
Lin, Horng-Chih
;
Lin, Zer-Ming
;
Huang, Tiao-Yuan
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this study, we proposed a new methodology for probing the electrical properties of heavily doped polycrystalline silicon (poly-Si) nanowires (NWs), including active doping concentration, mobility, and interface fixed charge density. Implementation of this procedure is based on the modulation of the device operation of a gate-all-around (GAA) junctionless (J-less) transistor from the gated resistor mode to the ungated one. The extracted carrier concentration in the NW is found to be much lower than that of Hall measurements, while a negative fixed charge density is identified with the procedure. Dopant segregation at the oxide interface is postulated to be closely related to these observations. (C) 2013 The Japan Society of Applied Physics
A study on low temperature transport properties of independent double-gated poly-Si nanowire transistors
(2010-10-29)
Chen, Wei-Chen
;
Lin, Horng-Chih
;
Lin, Zer-Ming
;
Hsu, Chin-Tsai
;
Huang, Tiao-Yuan
Employing mix-and-match lithography of I-line stepper and e-beam direct writing, independent double-gated poly-Si nanowire thin film transistors with channel lengths ranging from 70 nm to 5 mu m were fabricated and characterized. Electrical measurements performed under cryogenic ambient displayed intriguing characteristics in terms of length dependent abrupt switching behavior for one of the single-gated modes. Through simulation and experimental verification, the root cause for this phenomenon was identified to be the non-uniformly distributed dopants introduced by ion implantation.
A study on low temperature transport properties of independent double-gated poly-Si nanowire transistors
(2010-10-29)
Chen, Wei-Chen
;
Lin, Horng-Chih
;
Lin, Zer-Ming
;
Hsu, Chin-Tsai
;
Huang, Tiao-Yuan
Employing mix-and-match lithography of I-line stepper and e-beam direct writing, independent double-gated poly-Si nanowire thin film transistors with channel lengths ranging from 70 nm to 5 mu m were fabricated and characterized. Electrical measurements performed under cryogenic ambient displayed intriguing characteristics in terms of length dependent abrupt switching behavior for one of the single-gated modes. Through simulation and experimental verification, the root cause for this phenomenon was identified to be the non-uniformly distributed dopants introduced by ion implantation.
Analytical Model of Subthreshold Current and Threshold Voltage for Fully Depleted Double-Gated Junctionless Transistor
(2012-02-01)
Lin, Zer-Ming
;
Lin, Horng-Chih
;
Liu, Keng-Ming
;
Huang, Tiao-Yuan
;
電子工程學系及電子研究所
In this study, we derive an analytical model of an electric potential of a double-gated (DG) fully depleted (FD) junctionless (J-less) transistor by solving the two-dimensional Poisson's equation. On the basis of this two-dimensional electric potential model, subthreshold current and swing can be calculated. Threshold voltage roll-off can also be estimated with analytical forms derived using the above model. The calculated results of electric potential, subthreshold current and threshold voltage roll-off are all in good agreement with the results of technology computer aided design (TCAD) simulation. The model proposed in this paper may help in the development of a compact model for simulation program with integrated circuit emphasis (SPICE) simulation and in providing deeper insights into the characteristics of short-channel J-less transistors. (C) 2012 The Japan Society of Applied Physics
Characteristics of n-Type Asymmetric Schottky-Barrier Transistors with Silicided Schottky-Barrier Source and Heavily n-Type Doped Channel and Drain
(2012-06-01)
Lin, Zer-Ming
;
Lin, Horng-Chih
;
Huang, Tiao-Yuan
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this study, we explore the operation of operation a novel asymmetric Schottky-barrier transistor (ASSBT) through using technology computer aided design (TCAD). The new ASSBT features a silicided Schottky-barrier (SB) source, with the channel and drain made of heavily n-doped silicon. By eliminating the SB drain junction contained in conventional symmetrical-type SB metal-oxide-semiconductor field-effect transistors (MOSFETs), a larger on-state current is achievable. Moreover, combined with the adoption of fully depleted thin-film channel, the off-state leakage current can be efficiently suppressed as well. In addition, we also comprehensively analyze the transport mechanisms dominating in different operational regions of this new ASSBT. A pseudo-subthreshold region that shows worse subthreshold swing (SS) than the subthreshold region is identified. A decrease in channel and/or gate oxide thicknesses can contribute to the improvement of the SS of this region. A modified form of scaling length (lambda) is also introduced to describe the impacts of structural parameters and gate configurations on the SS characteristics of this new ASSBT. (c) 2012 The Japan Society of Applied Physics
Characteristics of Planar Junctionless Poly-Si Thin-Film Transistors With Various Channel Thickness
(2013-03-01)
Lin, Horng-Chih
;
Lin, Cheng-I
;
Lin, Zer-Ming
;
Shie, Bo-Shiuan
;
Huang, Tiao-Yuan
N-type junctionless (JL) planar poly-Si thin-film transistors (TFTs), which contain an in situ heavily phosphorous-doped channel with thickness ranging from 8 to 12 nm, were fabricated and characterized. The devices exhibit superior current drive and good control over performance variability. From C-V characterization, the ionized dopant concentration in the channel is determined to be around 2 x 10(19) cm(-3) and the fixed charge density to be around -6 x 10(12) cm(-2). The negative fixed charge density is probably related to the segregation of phosphorous species at the oxide/channel interface. We also observed a reverse short-channel effect from the relationship between the threshold voltage and the channel length. One mechanism considering enhanced phosphorous segregation is proposed to explain this finding.
Gate-All-Around Junctionless Transistors With Heavily Doped Polysilicon Nanowire Channels
(2011-04-01)
Su, Chun-Jung
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Tsai, Tzu-I
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Liou, Yu-Ling
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Lin, Zer-Ming
;
Lin, Horng-Chih
In this letter, we have investigated experimentally, for the first time, the feasibility of gate-all-around polycrystalline silicon (poly-Si) nanowire transistors with junctionless (JL) configuration by utilizing only one heavily doped poly-Si layer to serve as source, channel, and drain regions. In situ doped poly-Si material features high and uniform-doping concentration, facilitating the fabrication process. The developed JL device exhibits desirable electrostatic performance in terms of higher ON/OFF current ratio and lower source/drain series resistance as compared with the inversion-mode counterpart. Such scheme appears of great potential for future system-on-panel and 3-D IC applications.
Insight into the performance enhancement of double-gated polycrystalline silicon thin-film transistors with ultrathin channel
(2010-02-15)
Lin, Zer-Ming
;
Lin, Horng-Chih
;
Chen, Wei-Chen
;
Huang, Tiao-Yuan
;
電子工程學系及電子研究所
In this letter, characteristics of independently-controllable double-gated polycrystalline silicon (poly-Si) thin-film transistors (TFTs) with ultrathin channel are characterized and analyzed experimentally and theoretically. As compared with the single-gated mode where only one of the gates is used for driving the device, 1.3-2.1 fold increase in drive current is achieved under double-gated mode as the two gates are biased simultaneously for driving the device. A remarkable lowering of barrier height 7-12 meV in the latter case due to the coupling of the two gate biases is identified as the major origin for such performance enhancement.
Investigation of p-type junction-less independent double-gate poly-Si nano-strip transistors
(2014-01-01)
Liu, Keng-Ming
;
Lin, Zer-Ming
;
Wu, Jiun-Peng
;
Lin, Horng-Chih
;
Huang, Tiao-Yuan
In this study, novel independent double-gate (IDG) junction-less (J-less) polycrystalline silicon (poly-Si) nano-strip transistors have been fabricated and investigated. Inversion-mode (IM) IDG poly-Si nano-strip transistors with the undoped channel have also been fabricated for comparison. The experimental data show the superior on-state current of J-less transistors over that of IM transistors mainly due to the reduction of the channel resistance (R-ch). However, the drain-induced barrier lowering of the J-less transistors is larger than that of IM transistors but the double-gate (DG) configuration can mitigate this problem to some extent. Besides, the subthreshold swing and its fluctuation of the J-less transistors are worse than those of IM transistors under the single-gate operation. Fortunately, this issue can be significantly improved by the aid of DG configuration according to our experimental results. We also demonstrate the possibility of changing the threshold voltage (V-th) under IDG operation for the J-less IDG nano-strip transistors.
Origin of hysteresis in current-voltage characteristics of polycrystalline silicon thin-film transistors
(2009-03-01)
Lin, Horng-Chih
;
Hung, Cheng-Hsiung
;
Chen, Wei-Chen
;
Lin, Zer-Ming
;
Hsu, Hsing-Hui
In this work we report the observation and characterization of a hysteresis phenomenon in the transfer characteristics of n-channel polycrystalline silicon (poly-Si) thin-film transistors (TFTs). Such phenomenon is observed in devices with fully depleted channel and not treated with hydrogen-related anneal. The origin of the hysteresis is identified to be related to the electron trapping and detrapping processes associated with the deep-level traps in the grain boundaries of the poly-Si channel.
Read Characteristics of Independent Double-Gate Poly-Si Nanowire SONOS Devices
(2011-11-01)
Lin, Horng-Chih
;
Lin, Zer-Ming
;
Chen, Wei-Chen
;
Huang, Tiao-Yuan
;
電子工程學系及電子研究所
This paper investigates the read operation of poly-Si nanowire silicon-oxide-nitride-oxide-silicon devices with independent double-gate (IDG) configuration. The device features oxide-nitride-oxide (ONO) stack as the charge storage medium in one of the two gated sides with pure oxide in the other. Owing to the IDG feature, the shift in the device's transfer characteristics due to a change in the amount of storage charges can be sensed with two different modes, which have one of the two gates applied with a sweeping bias (driving gate) and the other with a fixed bias (control gate). Our analysis and experimental data show that a larger memory window is obtained when the gate of the ONO side is used as the driving gate. Moreover, the memory window of this mode is essentially independent of the bias applied to the control gate. Based on this finding, a novel Flash structure featuring IDG cells with a common control gate is proposed.