Browsing by Author "Lin Jhih-Yu"

Now showing 1 - 3 of 3

ASYMMETRIC VIRTUAL-GROUND SINGLE-ENDED SRAM AND SYSTEM THEREOF
(2012-03-08)
JOU Shyh-Jye
;
Lin Jhih-Yu
;
Chuang Ching-Te
;
Tu Ming-Hsien
;
Tsai Ming-Chien
The present invention discloses an asymmetric virtual-ground single-ended SRAM and a system thereof, wherein a first inverter is coupled to a high potential and a virtual ground, and wherein the first inverter and a second inverter form a latch loop, and wherein a third inverter is electrically connected with the second inverter, and wherein the third inverter and the second inverter are jointly coupled to the high potential and a ground. A write word line and a read word line control an access transistor and a pass transistor to undertake writing and reading of signals. A plurality of asymmetric virtual-ground single-ended SRAMs forms a memory system.
SINGLE-ENDED SRAM WITH CROSS-POINT DATA-AWARE WRITE OPERATION
(2013-08-01)
Jou Shyh-Jye
;
Lin Jhih-Yu
;
Chuang Ching-Te
;
Tu Ming-Hsien
;
Chiu Yi-Wei
A single-ended SRAM including at least one memory cell and a third switch is provided. The memory cell includes a data-latching unit, a first switch, a second switch and a data-transferring unit. The data-latching unit is configured for latching the received input data and provides a storage data and the inverse data of the storage data. The first switch transfers a reference data to the data-latching unit according to a first word-line signal. The second switch transfers the reference data to the data-latching unit according to a second word-line signal. The data-transferring unit decides whether or not to transfer the reference data to the bit-line according to the storage data and a control signal. The third switch receives the reference data and the control signal and transfers the reference data to the first switch, the second switch and the data-transferring unit according to the control signal.
Single-ended SRAM with cross-point data-aware write operation
(2014-04-08)
Jou Shyh-Jye
;
Lin Jhih-Yu
;
Chuang Ching-Te
;
Tu Ming-Hsien
;
Chiu Yi-Wei
A single-ended SRAM including at least one memory cell and a third switch is provided. The memory cell includes a data-latching unit, a first switch, a second switch and a data-transferring unit. The data-latching unit is configured for latching the received input data and provides a storage data and the inverse data of the storage data. The first switch transfers a reference data to the data-latching unit according to a first word-line signal. The second switch transfers the reference data to the data-latching unit according to a second word-line signal. The data-transferring unit decides whether or not to transfer the reference data to the bit-line according to the storage data and a control signal. The third switch receives the reference data and the control signal and transfers the reference data to the first switch, the second switch and the data-transferring unit according to the control signal.