Browsing by Author "Linten, Dimitri"

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Influence of InGaP and AlGaAs Schottky Layers on ESD Robustness in GaAs pHEMTs
(2012-09-01)
Chen, Shih-Hung
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Lin, Yueh-Chin
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Linten, Dimitri
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Scholz, Mirko
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Hellings, Geert
GaAs high-electron-mobility transistors (HEMTs) have been widely used for radio-frequency (RF) applications due to the excellent material properties. One of the essential elements of the HEMTs is the gate Schottky barrier layer. InGaP has been proposed and proven as a better Schottky barrier material for the RF performance of the GaAs HEMTs. This letter investigates the influence of the GaAs HEMTs with two different Schottky layers, which are InGaP and AlGaAs on device transient characteristics under electrostatic discharge (ESD) stress. Although InGaP presents significant advantages on improving RF performance of GaAs HEMTs, it shows inferiority in ESD robustness.
Local CDM ESD Protection Circuits for Cross-Power Domains in 3D IC Applications
(2014-06-01)
Chen, Shih-Hung
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Linten, Dimitri
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Scholz, Mirko
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Huang, Yu-Ching
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Hellings, Geert
CDM ESD events can be a potential threat to SoC designs or heterogeneous 3D ICs with multiple power domains. Inter-layer ( or interface) circuits may need a local CDM ESD clamp that can prevent the unexpected failure under CDM ESD stress. In this letter, two local CDM ESD clamp circuits are proposed. They show better clamping efficiency under 2-ns vfTLP stress.
RF/High-Speed I/O ESD Protection: Co-optimizing Strategy Between BEOL Capacitance and HBM Immunity in Advanced CMOS Process
(2020-07-01)
Wu, Wei-Min
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Ker, Ming-Dou
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Chen, Shih-Hung
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Chen, Jie-Ting
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Linten, Dimitri
In order to meet the requirement of ultrahigh-speed, low latency, and wide bandwidth (BW) in the next 5G mobile network and internet of things (IoT) applications, the parasitic capacitance specification of electrostatic discharge (ESD) protection devices should become much stricter. Reducing the capacitance always degrades the ESD performance in terms of shrinking the size of the ESD protection device. The distributed ESD protection network is one of the solutions which mitigates the capacitance issue and provides a broadband design. However, while the ESD devices are put under the I/O pad in the distributed ESD protection network, back-end-of-line (BEOL) capacitance starts to play an important role in the advanced 28-nm CMOS process. Therefore, a tapered metal structure is proposed to significantly reduce 30% BEOL capacitance of the ESD device, which can gain a 2.8-GHz increase in the operational BW in the distributed network. Meanwhile, it can enhance the human-body-model (HBM) level up to 16% higher than the original layout style under the same front-end-of-line (FEOL) layout size.