Browsing by Author "Liow, YY"

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New current-mode wave-pipelined architectures for high-speed analog-to-digital converters
(2004-01-01)
Wu, CY
;
Liow, YY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this paper, two new architectures for high-speed CMOS wave-pipelined current-mode A/D converters (WP-IADCs) are proposed and analyzed. In the new WP-IADC architectures, the wave-pipelined theory is applied to both pipeline structures, called full WP-IADC (FWP-IADC) and indirect transfer WP-IADC (ITWP-IADC). In the FWP-IADC, each stage uses the full current-mode wave-pipelined structure without switched-current cell circuits. In the ITWP-IADC, the switched-current cells are incorporated into the wave-pipelined stages which are divided into several sections with controlled clocks. Therefore, the proposed ITWP-IADC performs optimally in terms of speed and accuracy in the WP-IADCs. Generally, the proposed WP-IADCs have the advantages of high speed, high input frequency, high efficiency of timing usage, high clock-period flexibility in switched-current cells for precision enhancement, and reduced number of switched-current cells in the overall data path for linearity improvement. According to the theoretical analysis on the proposed WP-IADC structures, the minimum sampling clock period is proportional to the intrinsic delay of the current mirror and the increased rise/fall time in each wave-pipelined stage. The HSPICE simulation results reveal that, under Nyquist rate sampling in 8-b resolution, a sampling rate of 20 and 54 MHz can be achieved for FWP-IADC and two-section ITWP-LADC, respectively. If four wave-pipelined sections are used, the ITWP-IADC can be operated at 166 MHz at an input frequency of 8 MHz. To experimentally verify the correct function of the proposed WP-IADC structures, the proposed new architecture of the FWP-IADC is implemented by using 0.35-mum CMOS technology. The measurement results successfully demonstrate the feasibility of wave-pipelined IADC architectures in applications of high-speed ADCs.
The design of high-speed pipelined analog-to-digital converters using voltage-mode sampling and current-mode processing techniques
(2002)
Liow, YY
;
Wu, CY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this paper, a new structure of 8-bit CMOS pipelined analog-to-digital converter (ADC) is proposed and analyzed. In order to achieve a high conversion rate, the proposed new structure adopts voltage-mode open-loop sampling circuit and current-mode circuits to perform subtraction, sub-DAC operation, and comparison. Due to current-mode subtraction operation, the close-loop circuit can be avoided to improve the speed performance. Moreover, current steering sub-DAC is used to enhance the sub-DAC speed. From the simulation results on the demonstrative example, the proposed pipelined ADC architecture can achieve 8-bit accuracy with a sampling rate up to 71.4MS/s when the input signal frequency is 10M Hz. The power dissipation of the pipelined ADC is 205mW at the conversion rate of 71.4 MS/s with a single 3.3V power supply and 1P5M 0.25mum CMOS process. The proposed structure can reach a higher speed if the voltage-sampling delay is reduced.