Browsing by Author "Liu, C. H."

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A Novel Design of P-N Staggered Face-tunneling TFET Targeting for Low Power and Appropriate Performance Applications
(2017-01-01)
Hsieh, E. R.
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Fan, Y. C.
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Chang, K. Y.
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Liu, C. H.
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Chien, C. H.
A novel complementary tunneling FET (C-TFET) has been designed and targeted for the low power and appropriate performance applications (Apps). In this new architecture of C-TFET, the drain and source (D/S) are configured as a staggered structure to increase the tunneling current, and the conventional p-i-n junction C-TFET has been modified as a p-n junction to further enhance the I-on current. The results show that new design can achieve 310uA/um(n), 440uA/um(p) TFETs of I-on, comparable to those of LP planar CMOS devices, 0.1 nA/um of I-off, while excellent S.S.(<10mV/dec) at V-dd= 0.7V, which will be a promising candidate for the low-power and appropriate performance apps in the next decade.
A Novel ReWritable One-Time-Programming OTP (RW-OTP) Realized by Dielectric-fuse RRAM Devices Featuring Ultra-High Reliable Retention and Good Endurance for Embedded Applications
(2018-01-01)
Cheng, H. W.
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Hsieh, E. R.
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Huang, Z. H.
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Chuang, C. H.
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Chen, C. H.
A novel concept of OTP has been demonstrated to create another feasibility to allow re-writable capability before storing the data. This OTP is named ReWritable One-time programming (RW-OTP) memory. With RW-OTP, users can do the test by modifying the contexts repeatedly before finalizing the stored data. To implement the memory cell, it consists of a gate-floated FinFET and an RRAM where a bilayer has been designed as a thicker dielectric layer with resistive-switching property on a thinner dielectric-fuse layer. Moreover, the process of RW-OTP is fully compatible with the state-of-the-art CMOS logic technology. The result shows that the memory cell exhibits high retention and good endurance. With proper use of RW-OTP, the users can not only reduce error jobs cost-efficiently but also can develop various applications for their needs. This memory cell is very promising for embedded applications.
Design of Complementary Tilt-gate TFETs with SiGe/Si and III-V Integrations Feasible for Ultra-low-power Applications
(2015)
Hsieh, E. R.
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Lin, Y. S.
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Zhao, Y. B.
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Liu, C. H.
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Chien, C. H.
A new concept of the structure design with an alignment between the maximum band-to-band tunneling rate and electric field has been proposed to enhance the performance of TFETs. It was found that the specific gate of TFET to form an obtuse shape can dramatically improve the on-current of TFET, with over 4 order improvement in comparison to planar ones. This complementary TFET (CTFET) was also demonstrated by SRAM as a benchmark, with SiGe/Si integrated with III-V on Si substrate. In order to increase WNM and RSNM of CTFET SRAM, a new scheme has been adopted, in which SRAM has been successfully demonstrated with operating bias down to 0.3V.
Embedded PUF on 14nm HKMG FinFET Platform: A Novel 2-bit-per-cell OTP-based Memory Feasible for IoT Secuirty Solution in 5G Era
(2019-01-01)
Hsieh, E. R.
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Wang, H. W.
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Liu, C. H.
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Chung, Steve S.
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Chen, T. P.
In this work, a novel concept of 2-bit-per-cell (2B/C) is introduced to realize high-density OTP PUF from a new scheme of dielectric breakdown. This PUF shows 10(5)x of large window, good immunity to high-temperature disturbance, and excellent retention under 150 degrees C baking, which are particularly for automotive applications. In terms of security. this PUF exhibits near ideal normal distribution of hamming distance and narrow distribution of hamming weight. The bit error rates are low, 0.78% at 25 degrees C and 1.95% at 150 degrees C, benchmarked on a 256-bit array. Finally, the security test of this PUF against the hackers' attack from the machine learning process has been proved to have high security. Overall, the proposed 2B/C OTP PUF demonstrated great potential for IoT security in 5G era.
Geometric Variation: A Novel Approach to Examine the Surface Roughness and the Line Roughness Effects in Trigate FinFETs
(2017-01-01)
Hsieh, E. R.
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Fan, Y. C.
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Liu, C. H.
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Chung, Steve S.
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Huang, R. M.
A new theory has been developed for geometric variation of trigate FinFETs. This geometric variation includes both line roughness induced variation and oxide-thickness variation, which can be measured from gate capacitance and Ig current variations, respectively. Experimental results show that trigate devices are subject to serious line variations as the fin height scales up and the fin-width scales down, leading to large Ion current variation, i.e., as we increase the fin aspect-ratio, line variation becomes worse which shows an increase of the active power consumption. On the other hand, oxide-thickness variation reveals significant impacts on the off-state leakage, i.e., a rough gate oxide yields to larger static power. These valuable results provide us important guideline for the design and manufacturing of high quality 3D gate FinFETs.
High Efficiency E-coli Concentration via Dynamic Light-induced Optoelectro-osmosis Flow on Organic Photoconductivity Biochip
(2011)
Yang, S. M.
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Lin, C. Y.
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Wang, T. P.
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Punde, T. H.
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Chang, H. Y.
We demonstrate a dynamic light-induced optoelectro-osmosis flow design for high efficiency E. coli concentration on an organic photoconductive material based biochip. Several traditional approaches of bacteria purification and enrichment utilize magnetic beads coated with antibodies to attract them. The efficiency of collecting magnetic beads is equal to sort bacteria. Our work provides a direct method to enrich the E. coli concentration with dynamic light images. Due to the applications of photoconductive material, TiOPc, two features are demonstrated, simple biochip fabrication processes and rapid E. coli collection. The biochip is fabricated only with spin-coating a thin TiOPc layer, 500nm, on the indium tin oxide (ITO) conductive glass. Besides, the E. colt are concentrated together within 30 sec toward the illuminating region by the surface charge slip. We also calibrate the dominating effects in different applied AC frequency region. In conclusion, our light-induced E. coli manipulation approach would expand the scope of the examination efficiency, for example, water quality.
National Project on 45 to 32 nm Metal Oxide Semiconductor Field Effect Transistors for Next Century IC Fabrications
(2008)
Hwang, Huey-liang
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Wang, C. W.
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Chang, K. H.
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Tsai, C. H.
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Leou, K. C.
It is well known that the Taiwan Semiconductor industries play the very key roles for the worldwide IC foundry, and the advanced research of nanoelectronics is the lifeline for its long term developments. Professor Huey-liang Hwang effectively integrated the most outstanding research team and resource in Taiwan on the National Project on Nanometer CMOS Transistors for the 21 century, which is sponsored by the Ministry of Economic Affairs of ROC. A dozen of Professors from NTHU( National Tsing Hua University) with expertise at the novel materials and analysis and NCTU( National Chiao Tung University) with expertise at devices and reliability are devoted to the studies and are in collaboration with the world-wide-known company such as TSMC, and breakthrough of the key technologies of 45-32 nm technologies are achieved. The objective of this project is focused on the development of advanced metal gate/high-k MOSFET for 45 nm node generation and beyond, the efforts include the world first successful suppression the oxide/Si interfacial layer formation by using a bi-layer composite of HfO2 3.2 nm (ALD)/HfO2 1.5 nm (MBE), the results show a dielectric constant of 16 and an EOT of 1.15 nm, a Dit was estimated to be 4.6x10(11)cm(-2)eV(-1) with the leakage at Vfb-1V being 8.5x10(-6) A/cm(2). Also, the thermal stability of HfO2, HfAlOx alloy and Al2O3/HfO2 stack, prepared by ALD were compared, the incorporation of Al in alloy form gave superior characteristics by retaining an amorphous structure up to 1000 C, which suppress the leakage current and retards growth of the interfacial layer giving the least increment of EOT and interface traps. Besides, by incorporating Al into TiO2 gave an EOT value of the Al2O3/TiAlOx/Al2O3 film down to 0.8 nm. Furthermore, high selectivity was obtained via etching the HfAlO and silicon wafer with pattern using the ICP Plasma. In this project, YbSi metal gate for n-MOSFET and IrSi metal gate p-MOSFET were successfully fabricated for the HfAlON MESFET. The results showed the good effective workfunction of 4.15 and 4.9 eV and no degradation of gate dielectric current and mobility in the YbxSi/HfAlON and IrxSi/HfAlON FUSI-gates by reducing the metal diffusion at lower temperatures.
NUSAS: NEGATIVE PRESSURE DRIVING HEPG2/3T3 CELLS MIXING/GRADIENT CO-CULTURE INSIDE U TRAPPER ARRAY ON RAPID MULTICELLULAR SPHEROID ASSEMBLING SYSTEM
(2012)
Yang, S. M.
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Fu, C. Y.
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Tseng, S. Y.
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Srinivasu, V. P.
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Shilpa, S.
This article presents a Negative-pressure-powered U-trapper of Spheroid Assembling System (NUSAS) and four unique features are addressed: (1) Negative pressure powered medium driving, (2) HepG2/3T3 gradient distribution and mixing co-culture, (3) Cell trapping effect via gravity force and liquid flow co-activation, and (4) Large area of U trapper array. The development of in vitro liver device benefits liver toxicology and metabolism.[1,2] However, due to the complexity of human liver tissue, it has been rarely discussed what kind of hepatocyte to fibroblast ratio has nearest performance to a real liver tissue. Here, we culture liver/fibroblast cells with gradient ratio as multicellular assembling spheroids simultaneously to find this ratio. These results based on our efficient approaches give us meaningful foundations to investigate biomedical character of 3D HepG2/3T3 artificial tissue in different mixing cell conditions.
The Experimental Demonstration of the BTI-Induced Breakdown Path in 28nm High-k Metal Gate Technology CMOS Devices
(2014)
Hsieh, E. R.
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Lu, P. Y.
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Chung, Steve S.
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Chang, K. Y.
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Liu, C. H.
For the first time, the breakdown path induced by BTI stress can be traced from the RTN measurement. It was demonstrated on advanced high-k metal gate CMOS devices. RTN traps in the dielectric layers can be labeled as a pointer to trace the breakdown path. It was found that breakdown path tends to grow from the interface of HK/IL or IL/Si which is the most defective region. Two types of breakdown paths are revealed. The soft-breakdown path is in a shape like spindle, while the hard breakdown is like a snake-walking path. These two breakdown paths are reflected in a two slopes TDDB lifetime plot. These new findings on the breakdown-path formation will be helpful to the understanding of the reliability in HK CMOS devices.
The Observation of BTI-induced RTN Traps in Inversion and Accumulation Modes on HfO2 High-k Metal Gate 28nm CMOS Devices
(2014-01-01)
Wu, P. C.
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Hsieh, E. R.
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Lu, P. Y.
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Chung, Steve S.
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Chang, K. Y.
A comprehensive analysis on the BTI induced RTN traps in high-k(HK) CMOS devices have been investigated in inversion (inv.) and accumulation (acc.) modes. The combination of two modes for RTN measurement provides a wide range of energy window in high-k gate dielectric, in which a simple extraction method of RTN analysis has been adopted to analyze the gate dielectric dual-layer of advanced HK devices. The results show that inversion mode measurement can only identify the RTN traps in the channel region, which is related to the V-th degradation. While, accumulation mode may detect the traps inside the gate-drain overlap region which provides better understanding of GIDL current. This basic understanding is of critical important to the quality development of HK gate dielectrics in advanced CMOS technologies.
The Understanding of Gate Capacitance Matching on Achieving a High Performance NC MOSFET with Sufficient Mobility
(2019-01-01)
Chiang, C. K.
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Husan, P.
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Lou, Y. C.
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Li, F. L.
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Hsieh, E. R.
We develop experimental approaches to quantitatively extract the negative capacitance of MIM in a gate stacked NCFET. It was found that the NC effect is highly dependent on the grain and dipole behaviors with different annealing temperature. Also, to achieve a better design of high-performance NCFET, we explore not only the capacitance matching between ferroelectric HZO MIM and MOSFET but also how effective mobility is affected by HZO dipoles. For capacitance matching, we observe a 50x enhancement of overall gate capacitance triggered by NC effect, while, however, it adversely generated the degradation of the mobility. This mobility degradation is induced by the remote scattering from the ferroelectric HZO dipoles. Fortunately, if suitable polarization can be formed to align the HZO dipoles, the effects of remote scattering can be mitigated. From a trade-off between gate capacitance and the mobility, an NCFET with desirable performance can be achieved.