Browsing by Author "Liu, CNJ"

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A design-for-verification technique for functional pattern reduction
(2003-03-01)
Liu, CNJ
;
Chen, IL
;
Jou, JY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This technique reduces the number of required functional patterns by first defining conditions for hard-to-control (HTC) code in a hardware-description-language design and then using an algorithm to detect such code automatically. A second algorithm eliminates these HTC points by selecting a minimum number of nodes for control point insertion.
A novel approach for functional coverage measurement in HDL
(2000)
Liu, CNJ
;
Chang, CY
;
Jou, JY
;
Lai, MC
;
Juan, HM
While the coverage-driven functional verification is getting popular: a fast and convenient coverage measurement tool is necessary. In this paper, we propose a hovel approach for functional coverage measurement based on the VCD files produced by the simulators. The usage flow of the proposed dumpfile-based coverage analysis is much easier and smoother than that of existing instrumentation-based coverage tools. No pre-processing tool is required and no extra code will be inserted into the source code. Most importantly, the flexibility in choosing coverage metrics and measured code regions is increased. Only one simulation run is needed for any kind of coverage reports. By conducting some experiments on real examples: it shows very promising results in terms of the performance and the accuracy of coverage reports.
An automatic controller extractor for HDL descriptions at the RTL
(2000-07-01)
Liu, CNJ
;
Jou, JY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Extracting controlling finite-state machines can significantly reduce state space and thereby speed functional verification. The controller extraction algorithm uses an approach that frees it from restrictions on HDL code writing style.
An efficient design-for-verification technique for HDLs
(2001)
Liu, CNJ
;
Chen, IL
;
Jou, JY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Due to the high complexity of modern circuit designs, verification has become the major bottleneck of the entire design process. There is an emerging need for a practical solution to reduce the verification time. In manufacturing test, a well-known technique, "design-for-testability'', is often used to reduce the testing time. By inserting some extra circuits on the hard-to-test points, the testability can be improved and the testing time can be reduced. In this paper, we apply the similar idea to functional verification and propose an efficient "design-for-verification" (DFV) technique to help users reduce the verification time. The conditions for hard-to-control (HTC) codes in a HDL design are clearly defined, and an efficient algorithm to detect them automatically is proposed. Besides the HTC detection, we also propose an algorithm that can eliminate those HTC points with minimum number of DFV points. By the help of those DFV points, the number of required test patterns to reach the same coverage can be greatly reduced especially for deep-sequential designs.
An efficient IP-Level power model for complex digital circuits
(2003)
Hsu, CY
;
Liu, CNJ
;
Jou, JY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this paper, we propose an efficient IP-Level power model with a small lookup table for complex CMOS circuits. The table has only one dimension that maps the zero-delay charging and discharging capacitance into the real power consumption of pattern pairs but still has high accuracy. In order to improve the efficiency of the characterization process, the Monte Carlo approach is used during the estimation of the average power to skip the samples that will not increase the accuracy too much. The experimental result shows the table sizes are only up to 107 entries for ISCAS'85 benchmark circuits and the estimation error is only 2.99% on average using the lookup table.
An efficient power model for IP-level complex designs
(2003-08-01)
Hsu, CY
;
Liu, CNJ
;
Jou, JY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this paper, we propose an efficient IP-Level power model with a small lookup table for complex CMOS circuits. The table has only one dimension that maps the zero-delay charging and discharging capacitance (CDC) into the real power consumption of pattern pairs but still has high accuracy. In order to reduce the table size, we collect those pattern pairs with similar CDC values to be a group and only set an entry in the lookup table for each group. The proposed dynamic grouping process can automatically increase the entries of the lookup tables to cover the current CDC distribution of designs during the power characterization process. In order to improve the efficiency of characterization process, the Monte Carlo approach is used during the estimation for the average power of each group to skip the samples that will not increase the accuracy too much. After the power model of a circuit is built, the average power consumption for any test sequence can be estimated easily. The experimental result shows that the table sizes are only up to 107 entries for ISCAS'85 benchmark circuits and the estimation error is only 2.99% on average using this lookup table.
Automatic functional vector generation using the interacting FSM model
(2001)
Liu, CNJ
;
Yen, CC
;
Jou, JY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
While the coverage-driven design validation is getting popular, it would be more convenient for users to have an automatic generator that can generate the input patterns to satisfy the coverage requirements. The symbolic techniques can be used to generate the desired input patterns easily for a specific state transition in a FSM. However, it is not practical for real designs because the memory requirement is often unmanageable. In this paper, we propose an automatic pattern generation engine that can overcome the memory issues for large circuits. It can generate all possible input combinations or notify that such cases will never happen for any specific state transitions. Because we can reasonably partition the HDL designs into the interacting FSM model, the peak memory requirement can be significantly reduced by using the "divide and conquer" strategy for those small FSMs. The experimental results show that we can indeed generate the required input patterns with reasonable memory requirement for the designs with thousands of registers.
Effective error diagnosis for RTL designs in HDLS
(2002)
Jiang, TY
;
Liu, CNJ
;
Jou, JY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
We propose an effective approach to diagnose multiple design errors in HDL designs with only one erroneous test case. Error candidates will be greatly reduced while ensuring that true erroneous statements are included in, The probability of correctness for each potential erroneous statement will be estimated such that the most suspected statements are reported first. Experiments show that the size of error candidates is indeed small and the estimation for the probability of correctness for potential error candidates is accurate.
Efficient vector compaction methods for power estimation with consecutive sampling techniques
(2004-11-01)
Hsu, CY
;
Liu, CNJ
;
Jou, JY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
For large circuits, vector compaction techniques could provide a faster solution for power estimation with reasonable accuracy. Because traditional sampling approach will incur useless transitions between every sampled pattern pairs after they are concatenated into a single sequence for simulation, we proposed a vector compaction method with grouping and single-sequence consecutive sampling technique to solve this problem. However, it is very possible that we cannot find a perfect consecutive sequence without any undesired transitions. In such cases, the compaction ratio of the sequence length may not be improved too much. In this paper, we propose an efficient approach to relax the limitation a little bit such that multiple consecutive sequences are allowed. We also propose an algorithm to reduce the number of sequences instead of setting the number as one to find better solutions for vector compaction problem. As demonstrated in the experimental results, the average compaction ratio and speedup can be significantly improved by using this new approach.
Estimating likelihood of correctness for error candidates to assist debugging faulty HDL designs
(2005)
Jiang, TY
;
Liu, CNJ
;
Jou, JY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Debugging priority is a helpful technique to assist debugging faulty HDL designs [9]. However, debugging priority obtained by sorting confidence score is not good enough due to the inaccuracy in estimating likelihood of correctness for error candidates. Therefore, we developed Refined Confidence Score for deriving better debugging priority.
Improved vector compaction for power estimation with multi-sequence sampling technique
(2003)
Hsu, CY
;
Liu, CNJ
;
Jou, JY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A fast and accurate power estimation of circuits is definitely required when the low power issues become more and more important. For large circuits, vector compaction techniques could provide a fast solution for power estimation with reasonable accuracy. In previous work [11], we proposed an efficient vector compaction method with grouping and single-sequence consecutive sampling technique for CMOS circuits. The single-sequence approach improved the losses on compaction ratio and speedup by minimizing the useless transitions in traditional random or random-liked sampling approaches but it still involved some undesired transitions. In this paper, we propose a new consecutive sampling technique. multi-sequence approach. It can dramatically reduce the useless transitions without involving any undesired transitions. Compared to the random sampling and the single-sequence approaches, the experimental results demonstrate that the average compaction ratio and the average speedup can be significantly improved with our multi-sequence approach.