Browsing by Author "Liu, CW"

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A compact DSP core with static floating-point arithmetic
(2006-02-01)
Lin, TJ
;
Lin, HY
;
Chao, CM
;
Liu, CW
;
Jen, CW
A multimedia system-on-a-chip (SoC) usually contains one or more programmable digital signal processors (DSP) to accelerate data-intensive computations. But most of these DSP cores are designed originally for standalone applications, and they must have some overlapped (and redundant) components with the host microprocessor. This paper presents a compact DSP for multi-core systems, which is fully programmable and has been optimized to execute a set of signal processing kernels very efficiently. The DSP core was designed concurrently with its automatic software generator based on high-level synthesis. Moreover, it performs lightweight arithmetic-the static floating-point (SFP), which approximates the quality of floating-point (FP) operations with the hardware similar to that of the integer arithmetic. In our simulations, the compact DSP and its auto-generated software can achieve 3X performance (estimated in cycles) of those DSP cores in the dual-core baseband processors with similar computing resources. Besides, the 16-bit SFP has above 40 dB signal to round-off noise ratio over the IEEE single-precision FP, and it even outperforms the hand-optimized programs based on the 32-bit integer arithmetic. The 24-bit SFP has above 64 dB quality, of which the maximum precision is identical to that of the single-precision FP. Finally, the DSP core has been implemented and fabricated in the UMC 0.18 mu m 1P6M CMOS technology. It can operate at 314.5 MHz while consuming 52mW average power. The core size is only 1.5 mmx1.5 mm including the 16 KB on-chip memory and the AMBA AHB interface.
A dynamic normalization technique for decoding LDPC codes
(2005)
Liao, YC
;
Lin, CC
;
Liu, CW
;
Chang, HC
;
電子工程學系及電子研究所
In this paper, a dynamic normalization technique is proposed to approximate the nonlinear operation in decoding LDPC codes. The criterion in determining the normalization factor is also presented with theoretical analysis. The proposed method improves the approximation accuracy as well as the error performance of min-sum algorithm. Furthermore, the hardware implementation benefits from a simplified normalization scheme, leading to reductions in complexity and implementation loss.
A Laplace transform solution for tracer tests in a radially convergent flow field with upstream dispersion
(1996-09-01)
Chen, JS
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Liu, CW
;
Chen, CS
;
Yeh, HD
;
環境工程研究所
When tracers are introduced into an injection borehole, noticeable concentration gradients at the injection well may cause a backward spreading of the initial plume during radially convergent tracer tests. Based on this concept a non-rigorous mathematical model is developed to estimate the effect of backward spreading. The injection well with an instantaneous slug input is treated as a mathematical source and the initial plume at the injection well is allowed to move upstream. The model assumes that advection and longitudinal dispersion are the transport mechanisms in a radially converging how field. The Laplace transform solution for solute concentration in an infinite porous medium is obtained using the method of Green's function. Breakthrough curves are computed by numerically inverting the Laplace transform solution. As compared with the solution of Moench, it is concluded that the presence of backward movement of initial plume yields a decrease of peak concentration and spreading out of breakthrough curve tails. This effect is significant for small Peclet numbers and can be neglected for large Peclet numbers. A field tracer test is carried out to demonstrate the applicability of the model. The experimental data are fitted with the type curves of this study, and those of Moench's study, to determine dispersivity and aquifer porosity. The results show that dispersivity values estimated by matching the two type curves are different. Because it neglects backward dispersion, Moench's solution overestimates the dispersivity and effective aquifer porosity.
A Laplace transform solution for tracer tests in a radially convergent flow field with upstream dispersion
(1996-09-01)
Chen, JS
;
Liu, CW
;
Chen, CS
;
Yeh, HD
;
環境工程研究所
When tracers are introduced into an injection borehole, noticeable concentration gradients at the injection well may cause a backward spreading of the initial plume during radially convergent tracer tests. Based on this concept a non-rigorous mathematical model is developed to estimate the effect of backward spreading. The injection well with an instantaneous slug input is treated as a mathematical source and the initial plume at the injection well is allowed to move upstream. The model assumes that advection and longitudinal dispersion are the transport mechanisms in a radially converging how field. The Laplace transform solution for solute concentration in an infinite porous medium is obtained using the method of Green's function. Breakthrough curves are computed by numerically inverting the Laplace transform solution. As compared with the solution of Moench, it is concluded that the presence of backward movement of initial plume yields a decrease of peak concentration and spreading out of breakthrough curve tails. This effect is significant for small Peclet numbers and can be neglected for large Peclet numbers. A field tracer test is carried out to demonstrate the applicability of the model. The experimental data are fitted with the type curves of this study, and those of Moench's study, to determine dispersivity and aquifer porosity. The results show that dispersivity values estimated by matching the two type curves are different. Because it neglects backward dispersion, Moench's solution overestimates the dispersivity and effective aquifer porosity.
A novel register organization for VLIW digital signal processors
(2005)
Lin, TJ
;
Lee, CC
;
Liu, CW
;
Jen, CW
;
電子工程學系及電子研究所
This paper presents a novel register organization for VLIW DSPs. The simulation results show the performance of a DSP with the proposed register file is comparable with state-of-the-art DSPs. However, the proposed register file can save 89.7% area of a conventional centralized one, while reducing its access time by 68.6%.
Active devices under CMOS I/O pads
(2002-12-01)
Chou, KY
;
Chen, MJ
;
Liu, CW
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Active devices, including electrostatic discharge protection devices and ring-oscillator circuits, under CMOS I/O pads are investigated in a 130 nm full eight-level copper metal complementary metal-oxide-semiconductoir process, using fluorinated silicate glass (FSG) low-k inter-metal dielectric. The high current I-V curve measured in the second breakdown trigger point (V-t2, I-t2) of ESD protection devices under various metal level stack structures, shows that i) I-t2 depends very weakly on the number of metal levels used, as expected given specific junction power dissipation criteria; and ii) V-t2 increases with the number of metal level stacks of I/O pads because of increased dynamic impedance due to the presence of more metal levels, as clarified by a simple RC model. Moreover, no noticeable degradation in the speed of the ring-oscillator circuit, as measured for a variety of test structures subjected to bonding mechanical stress, thermal stress by temperature cycling and dc electrical stress by transmission line pulse, as well as ac electrical stress by capacitive-coupling experiments. Accordingly, active devices under CMOS I/O pads is independent of bonding pad metal level structures.
Architecture for area-efficient 2-D transform in H.264/AVC
(2005)
Kuo, YT
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Lin, TY
;
Liu, CW
;
Jen, CW
;
電子工程學系及電子研究所
As the VLSI technology advances continuously, ASIC can easily achieve the required performance and most of them are actually over-designed. Thus, architecture shrinking is inevitable in optimal designs especially when supply voltages are getting lower. However, conventional designs starting from minimization of algorithmic operations (e.g. multiply) may not always lead to optimal architectures, for the wires and the interconnection complexity significantly grow and have become predominant. This paper explores algorithms and architectures for the 2-D transform in H.264/AVC, of which the operations are very simple (i.e. only shift and add). We have shown that fewer operations do not always result in more compact designs. In our experiments with the UMC 0.18 mu m CMOS technology, the most straightforward matrix multiplication without separable 2-D operation or any fast algorithm has the best area efficiency for D1-size (720x480) video at 30fps. It saves 48%, 34% and 16% silicon area of the previous works respectively.
Characteristics of YBa2Cu3O7 thin films deposited on substrates buffered by various TiO2 layers
(2001-04-15)
Lin, PL
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Liu, CW
;
Hsieh, CC
;
Wu, KH
;
Juang, JY
Titanium nitride (TiN) and superconducting YBa2Cu3O7 (YBCO) thin films have been deposited sequentially on SrTiO3(STO)(100) substrates by in situ pulsed laser ablation. The TiN films were originally intended to serve as the lower contact electrode of the c-axis YBCO thin films. It was found that, although high-quality YBCO films could be obtained with the YBCO/TiN/STO(100) bilayer structure, the TiN(100) layer was oxidized which changed the structure into YBCO/TiO2/STO(100) during YBCO deposition. Comparative studies of depositing YBCO films directly onto a dc-sputtered TiO2/STO(100) template conventionally used in the selective epitaxial growth (SEG) process have, however, resulted in formation of a nonsuperconducting YBCO top layer. The characteristics of the resultant TiO2 layers obtained using various processes were analyzed to delineate the apparent discrepancies.
Characterization and reliability of low dielectric constant fluorosilicate glass and silicon rich oxide process for deep sub-micron device application
(2001-11-01)
Cheng, YL
;
Wang, YL
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Liu, CW
;
Wu, YL
;
Lo, KY
Fluorosilicate Glass (FSG) with low dielectric constant currently has been replaced as an alternative to SiO2 for device speed improvement. However, several integration aspects, such as Fluorine (F) distribution, F thermal stability, gap fill capability, capacitance reduction and via resistance of FSG prepared by the high density plasma (HDP) chemical vapor deposition (CVD) method are of concern for sub-0.18-mum devices. In this study, HDP-FSG films show different F concentrations at different locations on an 8-inch wafer. In addition, the FSG film shows poor thermal stability and F diffuses out of the film after high temperature annealing and the pressure cook test (PCT). However, the thermal stability of FSG film can be improved by capping with an oxide layer. The results indicate that silicon rich oxide (SRO) has a better effect at blocking the F diffusion out of FSG films at high temperature than plasma enhanced oxide (PE-OX). For the gap fill capability, HDP-FSG can fill all 0.23-mum gaps and some of the 0.21-mum gaps with an aspect ratio <3.8 but not the 0.19-mum gaps. A 8000 Angstrom HDP-FSG film with 600 Angstrom USG liner and 2000 Angstrom cap layer shows approximately 7.5 to 7.7% capacitance reduction on 0.23/0.23-mum gaps when compared with USG (undoped silicate glass). In addition, FSG has a larger capacitance reduction on the wider metal lines than the thinner metal lines at the same gap size due to a capacitance fringe effect. The via resistance for 0.26 mum unlanded via (which allow minor photo mis-alignment) of HDP-FSG film is also similar to that of USG. (C) 2001 Elsevier Science B.V. All rights reserved.
Chemical mechanical polishing of PSG and BPSG dielectric films: The effect of phosphorus and boron concentration
(1995-12-01)
Liu, CW
;
Dai, BT
;
Yeh, CF
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Chemical-mechanical polishing of blanket and patterned oxide films doped with phosphorus and boron has been studied. FTIR was used to characterize the film microstructure. Experimental results show that an increase of phosphorus level promoted the polish rate of PSG film. We also found that increasing the boron content enhanced the polish rate of BPSG films although phosphorus contents is decreased. This implies that boron is more effective than phosphorus in enhancing the polishing rate of BPSG films. However, the hardness of these doped films is slightly affected by doping level. Excellent planarity achieved by CMP is demonstrated for patterned wafers. Here, we also identify inversion patterns for the composite dielectric formed by a thin hard film on the top of a thick soft film. Such inversion phenomenon can be used for monitoring CMP process as a means of end point detection.
Complexity-aware design of DA-based fir filters
(2004)
Chen, CC
;
Lin, TJ
;
Liu, CW
;
Jen, CW
;
電子工程學系及電子研究所
This paper presents a novel technique to reduce the area of the hardwired lookup table (LUT) of DA-based FIR filters. It explores the optimal quantization on the real-valued LUT with optimal global scaling and error distribution, and we apply an effective error measure to estimate the quantization error on the FIR coefficients. Our approach enables designers to explicitly trade the quality for simple implementations at finer granularity than that solely by reducing the coefficient wordlengths. Moreover, in our simulations, the proposed method can save 30%similar to 40% silicon area of conventional DA-based FIR filters under identical error constraints.
Copper surface protection with a completely enclosed copper structure for a damascene process
(2004-01-30)
Wang, TC
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Hsieh, TE
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Wang, YL
;
Wu, YL
;
Lo, KY
As integrated circuit manufacture moving to copper interconnection for the most advanced products, protection of copper (Cu) surfaces becomes a major challenge for the back-end-of-line manufacturing process. The damages on Cu, such as Cu corrosion and oxidation, are often observed on wafers when exposing bare Cu surface in the presence of moisture and/or acidic gases. Furthermore, the Cu oxide results in poor adhesion both at Cu/barrier layer and Cu/stop layer interfaces. In this work, a novel Cu dual damascene structure which completely encloses the Cu surface with a tantalum nitride layer is presented. This capping layer avoids the Cu corrosion and oxidation due to its ability to keep moisture and acid off and away from the Cu surface. (C) 2003 Elsevier Science B.V. All rights reserved.
Effects of mechanical characteristics on the chemical-mechanical polishing of dielectric thin films
(1996-12-15)
Tseng, WT
;
Liu, CW
;
Dai, BT
;
Yeh, CF
;
電子工程學系及電子研究所
The effects of as-deposited (intrinsic) stress, externally applied (extrinsic) stresses, hardness, and modulus of various dielectric firms on chemical-mechanical polishing (CMP) removal and post-CMP cleaning processes are studied in this article. Intrinsic stresses of the polished dielectrics do not contribute directly to the CMP removal rate. Extrinsic stresses including normal and shear components are calculated using principles of elasticity and fluid mechanics respectively and their roles in the material removal process are discussed. Theoretical evaluation and experimental results both suggest that hardness and modulus are the two most important material characteristics affecting the CMP process. Efficiency of post-CMP particle extraction can be monitored using an adhesion probability which is related to the hardness of wafer and pad. Tn addition, particle removal rate can be remarkably enhanced by increasing pressure (normal stress) while increasing pad rotation speed (shear stress) contributes little to reduce the particle count.
Evaluation of advanced chemical mechanical planarization techniques for copper damascene interconnect
(2004-01-30)
Chen, KW
;
Wang, YL
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Liu, CP
;
Yang, K
;
Chang, L
According to rapid development of CMP technology, the difference of polishing methods would be applied for copper damascene interconnect. These methods include conventional rotary, linear, oscillation platform. The advantages of these platform would highlighted in uniformity control, stability of removal rate, planarization efficiency, throughput promotion, lower cost of ownership, even dishing and erosion effect integrated with slurry. This paper presented our experience to compare the uniformity, removal rate and planarization efficiency of Cu-CMP between various polishing platforms. In convection, the rotary or oscillation platform would be usually applied in oxide and tungsten CMP, due to the robust air-back carrier and rigid platen to polish the wafer, which performs the good reliability on wafer-to-wafer thickness and endpoint detection. However, the linear polisher is made of the air-bearing moving belt and self-rotated carrier and would provide the wider uniformity and planarization control window than others. In addition,, the simulation model would explain the difference from mechanic design and wafer moving paths between various polishing techniques. Hence, the trade-off advantage and application between various platforms would be compensated and integrated with slurry, conditioners and coming thickness profile from copper plating. It can achieve the optimization of Cu-CMP process. (C) 2003 Elsevier B.V. All rights reserved.
Hierarchical instruction encoding for VLIW digital signal processors
(2005)
Liu, CH
;
Lin, TJ
;
Chao, CM
;
Hsiao, PC
;
Lin, LC
VLIW-based architectures are very popular in high-performance DSP processors, for their relatively simpler implementations and more predictable execution times. But they need more program memory because of (1) the fixed-length instruction encoding, (2) NOP insertion due to limited parallelism, and (3) repetitive codes for loop unrolling. This paper describes a novel hierarchical instruction encoding that address these three problems to improve the VLIW code density. In our simulations, the proposed encoding scheme saves 61.4%-66.9% code sizes in highly parallel DSP kernels, and more savings can be expected for general programs. Besides, a simple decoding architecture is proposed and has been integrated into a 4-way VLIW DSP processor. The prototype is implemented in the 0.18um CMOS technology with its operating frequency at 208MHz.
Integration of a stack of two fluorine doped silicon oxide film with ULSI interconnect metallization
(2004-01-15)
Cheng, YL
;
Wang, YL
;
Liu, CP
;
Wu, YL
;
Lo, KY
Recently, fluorosilicate glass (FSG) has received much attention for application in microelectronics manufacturing due to its low dielectric constant and stable gap-filling ability. Although FSG films have been demonstrated as potential inter metal dielectrics (IMD) for sub-micron devices, integrating a stack of two fluorine doped silicon oxide film deposited on a high-density plasma chemical vapor deposition (HDP-CVD) system for gap filling and a plasma-enhanced chemical vapor deposition (PECVD) system for throughput has not been fully investigated. In this research, an excellent and exceptionally stable process was demonstrated for a stack of HDP-CVD FSG and PECVD FSG layers. Cracks that result from multi-level metal technology were eliminated when higher compressive stress PECVD FSG film was implemented as a capping layer. An 11% capacitance reduction was achieved when comparing a stack of FSG films to undoped silicon oxide. No problem occurred for photo, via etching and chemical mechanical polishing of FSG film. The FSG layer stack's via resistance (Rc(-)Via) as well as a full HDP-FSG scheme is comparable. These results are very promising for the integration of FSG films as inter metal dielectric for devices. (C) 2003 Elsevier B.V. All rights reserved.
Integration of MOCVD titanium nitride with collimated titanium and ion metal plasma titanium for 0.18-mu m logic process
(2001-11-01)
Lan, JK
;
Wang, YL
;
Lo, KY
;
Liu, CP
;
Liu, CW
Both collimated titanium (CO-Ti) and ion metal plasma titanium (IMP-Ti) have been widely used for plug liner layers. The focused ion beam (FIB) images of these films show that the IMP-Ti surface is granular and the CO-Ti surface is amorphous. It is concluded that the lower reflectivity and resistivity of IMP-Ti films are caused by the fact that IMP-Ti has a larger grain than that of the CO-Ti films. We define a grain size factor (GF) and find that the activation energy of grain growth of IMP-Ti film is 3.8 times larger than that of CO-Ti film. The electric measurement of vias resistance shows that IMP-Ti plug liner gives 13.6% higher via resistance and broader distribution than that of the CO-Ti plug liner. From the experimental data, we can conclude that there are three factors that make the IMP Ti plug liner process have higher vias resistance. These three factors are IMP-Ti resistivity, IMP-Ti thickness and CVD TiN thickness. (C) 2001 Elsevier Science B.V. All rights reserved.
Lightweight arithmetic units for VLSI digital signal processors
(2005)
Ou, SH
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Lin, TJ
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Lin, HY
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Chao, CM
;
Liu, CW
This paper presents a lightweight arithmetic for embedded signal processing, whose hardware complexity is similar to that of the integer one. In our simulations, its 16-bit version has 40.18dB signal to round-off error ratio over the IEEE single-precision floating-point arithmetic, which even out-performs the hand-optimized 32-bit code with integer arithmetic.
Mechanisms of circular defects for shallow trench isolation oxide deposition
(2003-09-01)
Lan, JK
;
Wang, YL
;
Liu, CP
;
Chao, CG
;
Ay, CY
Shallow trench isolation (STI) is extensively used as the isolation method beyond 0.18 mum generation. This study explored the formation of circular defects in high-density plasma (HDP) STI deposition. Circular defects were caused by the burst flow of silane reactive gas. The defect maps were coincident with the silane flow field. Fourier transform infrared and secondary-ion-mass spectroscopy data exhibited that the silane-burst flow formed a silicon rich oxide (SRO) film. This SRO film existed between the STI oxide and liner oxide. The circular defects were easily found using optical microscopy (OM) for STI with SRO film. Scanning electron microscopy and transmission electron microscopy photographs show that these defects include bubbles and concavities. When SRO fully covers the liner oxide, bubbles easily form by delamination between SRO film and liner oxide. This correlates with the high tensile stress produced by the SRO film. Besides this, higher STI deposition temperatures yield more bubbles. When SRO discontinuously forms on the liner oxide, the concavities were induced by the variation of STI deposition rate on SRO film and liner oxide. The surface charge difference between the SRO film and the liner oxide is the driving force for the generation of concavities. (C) 2003 American Vacuum Society.
Modeling of the wear mechanism during chemical-mechanical polishing
(1996-02-01)
Liu, CW
;
Dai, BT
;
Tseng, WT
;
Yeh, CF
;
電子工程學系及電子研究所
A model based on statistical method and elastic theory is presented to describe the wear mechanism of the silicon wafer surface during chemical-mechanical polishing. This model concerns the effects of applied pressure and relative velocity between the pad and the wafer on the removal rate during polishing and is capable of delineating the role of the mechanical properties of the slurry particles and the films to be polished. The removal rate is dependent on the elastic moduli of slurry particle and polished film. Comparisons with experimental data demonstrate the validity of the model for predicting relative removal rate for various dielectric films.