Browsing by Author "Liu, Chih Wei"

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Binaural-Cue-Based Noise Reduction Using Multirate Quasi-ANSI Filter Bank for Hearing Aids
(2016)
Tang, Huei-Shiuan
;
Yang, Cheng-Yen
;
Liu, Chih Wei
;
Chien, Chia-Cheng
;
電子工程學系及電子研究所
This paper presents a low-power and real-time noise reduction (NR) algorithm using 18-band 1/3-octave quasi-ANSI filter bank for binaural hearing aids. With aids of binaural cues and minima controlled recursive average (MCRA) approach, the proposed NR algorithm consists of a directional mask and an estimated mask. The directional mask exploits the interaural time difference (ITD) together with the interaural level difference (ILD) of two input sources to attenuate the lateral noise, while the estimated mask is used to further reduce the background noise and the coherence noise. Investigated by the circumstances with the -3 dB, 0 dB, and 3 dB, respectively, cocktail-party effect, the simulation results show that the proposed binaural NR algorithm gains an average of approximately 5.07 dB SNR improvement. Moreover, the speech intelligibility index (SII performance is superior, comparing that with the state-of-the-art NR algorithms for hearing aids. The proposed binaural NR algorithm has been implemented in TSMC 90 nm CMOS high-VT technology. The chip design is operated by 288 KHz and consumes approximately 121.6 mu W (@1 V). The chip design can be operated by 0.6 V for real-time processing 24 kHz audio. The simulated power consumption is approximately 64.52 W for binaural hearing aids.
Multithreaded coprocessor interface for multi-core multimedia SoC
(2008)
Ou, Shih-Hao
;
Lin, Tay-Jyi
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Deng, Xiang Sheng
;
Zhuo, Zhi Hong
;
Liu, Chih Wei
Modern architectures exploit task level parallelism to improve their performance in a cost-effective manner. However, task synchronization and management Is time consuming and wastes computing resources especially on application-specific architectures, such as DSP. In this paper, we propose a smart coprocessor interface that helps to offload the task management job from MPU or DSP. In our simulations, our approach can improve the overall performance of a dual-core platform by 57%. The hardware overhead of the interface is only 1.56% of the DSP core.