Browsing by Author "Liu, Chih-Hao"

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11.25-ms-Group-Delay and Low-Complexity Algorithm Design of 18-Band Quasi-ANSI S1.11 1/3 Octave Digital Filterbank for Hearing Aids
(2015-06-01)
Lai, Shin-Chi
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Liu, Chih-Hao
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Wang, Ling-Yi
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Chen, Shin-Hao
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Chen, Ke-Horng
This paper presents a novel algorithm and architecture design for 18-band quasi-class-2 ANSI S1.11 1/3 octave filterbank. The proposed design has several advantages such as lower group delay, lower computational complexity, and lower matching error. The technique we developed in this paper can be summarized as follows: 1) a simple low-pass filter (LPF) and discrete cosine transform (DCT) modulation are utilized to generate a uniform 9-band filterbank first, and then all elements of are replaced by all-pass filters to obtain a non-uniform filterbank; 2) a fast recursive structure and variable-length algorithm is further developed to efficiently accomplish DCT modulation. Thus, the spectrum of LPF can be easily spanned and flexibly extended to the location of the desired central frequency; 3) after employing the multi-rate algorithm, an 18-band non-uniform filterbank is generated from two 9-band sub filterbanks by following the proposed design steps and parameter determinations. Compared with the latest Liu et al.\'s quasi-class-2 ANSI S1.11 design, the proposed method-I (Proposed-I) totally has 72.8% reduction for multiplications per sample, 11.25-ms group delay, and 59 additions decreased per sample. Moreover, the maximum matching error of the proposed method-II (Proposed-II) is averagely equal to 1.79 dB much smaller than that of the latest Wei et al.\'s design. For the proposed variable-length DCT modulation, only 2 adders, 2 multipliers, 2 multiplexers, and 5 registers are required for hardware implementation after applying VLSI retiming scheme. Overall, the proposed filterbank design would be a new solution for future applications in the area of hearing aids.
An LDPC decoder chip based on self-routing network for IEEE 802.16e applications
(2008-03-01)
Liu, Chih-Hao
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Yen, Shau-Wei
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Chen, Chih-Lung
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Chang, Hsie-Chia
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Lee, Chen-Yi
An LDPC decoder chip fully compliant to IEEE 802.16e applications is presented. Since the parity check matrix can be decomposed into sub-matrices which are either a zero-matrix or a cyclic shifted matrix, a phase-overlapping message passing scheme is applied to update messages immediately, leading to enhance decoding throughput. With only one shifter-based permutation structure, a self-routing switch network is proposed to merge 19 different sub-matrix sizes as defined in IEEE 802.16e and enable parallel message to be routed without congestion. Fabricated in the 90 nm 1P9M CMOS process, this chip achieves 105 Mb/s at 20 iterations while decoding the rate-5/6 2304-bit code at 150 MHz operation frequency. To meet the maximum data rate in IEEE 802.16e, this chip operates at 109 MHz frequency and dissipates 186 mW at 1.0 V supply.
Design of a Multimode QC-LDPC Decoder Based on Shift-Routing Network
(2009-09-01)
Liu, Chih-Hao
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Lin, Chien-Ching
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Yen, Shau-Wei
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Chen, Chih-Lung
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Chang, Hsie-Chia
A reconfigurable message-passing network is proposed to facilitate message transportation in decoding multimode quasi-cyclic low-density parity-check (QC-LDPC) codes. By exploiting the shift-routing network (SRN) features, the decoding messages are routed in parallel to fully support those specific 19 and 3 submatrix sizes defined in IEEE 802.16e and IEEE 802.11n applications with less hardware complexity. A 6.22-mm(2) QC-LDPC decoder with SRN is implemented in a 90-nm 1-Poly 9-Metal (1P9M) CMOS process. Postlayout simulation results show that the operation frequency can achieve 300 MHz, which is sufficient to process the 212-Mb/s 2304-bit and 178-Mb/s 1944-bit codeword streams for IEEE 802.16e and IEEE 802.11n systems, respectively.
ISI-free block transceivers for unknown frequency selective channels
(2007-04-01)
Liu, Chih-Hao
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Phoong, See-May
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Lin, Yuan-Pei
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電控工程研究所
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Institute of Electrical and Control Engineering
The orthogonal frequency-division multiplexing (OFDM) transceiver has enjoyed great success in many wideband communication systems. It has low complexity and robustness against channel-induced intersymbol interference (ISI). When the channel order does not exceed the length of cyclic prefix, any frequency-selective channel is converted to a set of frequency-nonselective subchannels. This channel-independent ISI-free property is useful for many applications. In this correspondence, we study general block transceiver with such a property. We will show that the solutions of channel-independent ISI-free block transceivers are given in a closed form. It is found that except for some special cases, the solutions are identical to the Lagrange-Vandermonde and Vandermonde-Lagrange transceivers.
Method and apparatus for switching data in communication system
(2008-08-21)
Lee, Chen-Yi
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Liu, Chih-Hao
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Lin, Chien-Ching
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Chang, Hsie-Chia
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Hsu, Yar-Sun
A method and apparatus for switching data in communication system which comprises of mainly a conversion circuit to receive source data possessing real coding dimension and covert it to converted data possessing tolerable coding dimension; judgment bit is set in the converted data to designate the data as source data or not. Later on, shift circuit is used to shift the converted data in certain amount so as to generate a shifted data; meanwhile, the lowest bit and highest bit of shifted data are used to start acquiring real coding dimension to be used respectively as a first data and a second data, or by changing the pattern of acquiring the first data, then the highest bit minus the real coding dimension bit as the starting bit of the first data, and acquiring the real coding dimension from the side of the lowest bit. Finally, a comparison and selection circuit is used to compare the corresponding judgment bit in the first and the second data and to output an output data, wherein output data is source data with the above-mentioned amount of shift.
Multi-mode message passing switch networks applied for QC-LDPC decoder
(2008)
Liu, Chih-Hao
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Lin, Chien-Ching
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Chang, Hsie-Chia
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Lee, Chen-Yi
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Hsu, Yarsun
The multi-mode message passing switch networks for multi-standard QC-LDPC decoder are presented. An enhanced self-routing switch network with only one barrel shifter permutation structure and a shifter-based two-way duplicated switch network are proposed to support 19 and 3 different submatrices defined in IEEE 802.16e and IEEE 802.11n. These proposed switch networks can route the decoding message in parallel by different sizes without signal congestion. The enhanced self-routing switch network can switch the messages at different expansion factors with the lowest hardware complexity. Under the condition of a smaller expansion factor, the decoder throughput can be enhanced from the two-way duplicated switch network by increasing the parallelism. In the 130nm CMOS synthesis result, the proposed enhanced self-routing and the two-way duplicated switch network gate counts are 21.9k and 37.4k at 384MHz operation frequency.
On the design of cmfb transceivers for unknown channels
(2006)
Liu, Chih-Hao
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Phoong, See-May
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Lin, Yuan-Pei
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電控工程研究所
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Institute of Electrical and Control Engineering
In this paper, we consider the cosine modulated filter bank (CMFB) transceiver for unknown channels. Although it is a CMFB transceiver, the only channel dependent part of the transceiver is a set of scalar Multipliers at the receiver, like the OFDM. We show how to optimize the transmit and receive prototype filters so that the signal to interference ratio (SIR) is maximized. Moreover a new objective function that can incorporate the frequency response criteria is proposed. Simulation results show that we can obtain CMFB transceivers with high SIR values and good frequency responses.