Browsing by Author "Liu, Chih-Wei"

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10-ms 18-Band Quasi-ANSI S1.11 1/3-Octave Filter Bank for Digital Hearing Aids
(2013-03-01)
Liu, Chih-Wei
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Chang, Kuo-Chiang
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Chuang, Ming-Hsun
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Lin, Ching-Hao
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電子工程學系及電子研究所
The ANSI S1.11 1/3-octave filter bank is suitable for digital hearing aids, but its large group delay and high computational complexity complicate matters considerably. This study presents a 10-ms 18-band quasi-ANSI S1.11 1/3-octave filter bank for processing 24 kHz audio signals. We first discuss a filter order optimization algorithm to define the quasi-ANSI filters. The group delay constraint of filters is limited to 10 ms. The proposed design adopts an efficient prescription-fitting algorithm to reduce inter-band interference, enabling the proposed quasi-ANSI filter bank to compensate any type of hearing loss (HL) using the NAL-NL1 or HSE prescription formulas. Simulation results reveal that the maximum matching error in the prescriptions of the mild HL, moderate HL, and severe-to-profound HL is less than 1.5 dB. This study also investigates the complexity-effective multirate IFIR quasi-ANSI filter bank. For an 18-band digital hearing aid with a 24 kHz sampling rate, the proposed architecture eliminates approximately 93% of the multiplications and up to 74% of the storage elements, compared with a parallel FIR filters architecture. The proposed analysis filter bank (AFB) was designed in UMC 90 nm CMOS high-VT technology, and on the basis of post-layout simulations, it consumes 73 mu W (@V-DD = 1 V). By voltage scaling (to 0.6 V), the simulation results show that the power consumption decreases to 27 mu W, which is approximately 30% of that consumed by the most energy-efficient AFB available in the literature for use in hearing aids.
A 52mW 1200MIPS compact DSP for multi-core media SoC
(2006)
Ou, Shih-Hao
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Lin, Tay-Jyi
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Huang, Chao-Wei
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Kuo, Yu-Ting
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Chao, Chie-Min
This paper presents a DSP core for multi-core media SoC, which is optimized to execute a set of signal processing tasks very efficiently. The fully-programmable core has a data-centric instruction set and a corresponding latency-insensitive microarchitecture, where the hardware design is optimized concurrently with its automatic software generator. The proposed DSP core has 3X performance (in cycles) of those found in commercial dual-core application processors with similar computing resources. The silicon implementation in UMC 0.18 mu m 1P6M CMOS technology operates at 314MHz and consumes only 52mW average power.
A controllable low-power dual-port embedded SRAM for DSP processor
(2008)
Yang, Hao-I
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Chang, Ming-Hung
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Lin, Tay-Jyi
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Ou, Shih-Hao
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Deng, Siang-Sen
In this paper, a low-power embedded memory module is designed for a multi-threaded DSP processor. A codesign of circuit and architecture technique is proposed. The technique includes three circuit schemes: controllable precharged bit-line, low voltage bit-line, and controllable data-retention power gating. Because the low-power control signals are generated by the DSP engine, the operating condition of the memory module can be arbitrarily adjusted by using software programming. The integration of low-power dual-port 8KB SRAM and the multi-threaded DSP engine is implemented in TSMC 130nm CMOS technology. By using these techniques, the overall access power reduction of the DSP core is around 15.30%-16.84%.
A Low Power Hearing Aid Computing Platform Using Lightweight Processing Elements
(2012)
Chang, Kuo-Chiang
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Chen, Yu-Wen
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Kuo, Yu-Ting
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Liu, Chih-Wei
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電子工程學系及電子研究所
This paper presents a power-efficient computing platform for hearing aids. The proposed platform composes four heterogeneous processing elements. Each processing element includes one tiny RISC processor and several power-efficient hardwired accelerators. The hardwired accelerators integrate static floating-point and truncated multiplier to improve signal-to-noise ratio and reduce computational complexity. Compared to the post-truncate multiplication in FIR filter, the proposed static floating-point datapath reduces 50.8% area and improves 2.2 dB SNR simultaneously.
A Low-Error and Rom-Free Logarithmic Arithmetic Unit for Embedded 3D Graphics Applications
(2013)
Lin, Tsung-Ching
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Chen, Shin-Kai
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Liu, Chih-Wei
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
As the evolution of smart phone, 3D graphics become more and more important in mobile computing systems. Within 3D graphics, logarithmic arithmetic is usually utilized to simplify multiplication, division, and power operations. In this paper, we propose a low-error and Rom-free logarithmic arithmetic unit for 3D graphics applications. The logarithmic arithmetic unit applies non-uniform regional linear interpolation and compensation method for logarithmic converters. According to experiment results, proposed 2-region logarithmic converter reduces 48.0% error range and 42.1% percent error. 21.6% area and 13.8% power consumption are gained.
A Low-Error and Rom-Free Logarithmic Arithmetic Unit for Embedded 3D Graphics Applications
(2013-01-01)
Lin, Tsung-Ching
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Chen, Shin-Kai
;
Liu, Chih-Wei
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
As the evolution of smart phone, 3D graphics become more and more important in mobile computing systems. Within 3D graphics, logarithmic arithmetic is usually utilized to simplify multiplication, division, and power operations. In this paper, we propose a low-error and Rom-free logarithmic arithmetic unit for 3D graphics applications. The logarithmic arithmetic unit applies non-uniform regional linear interpolation and compensation method for logarithmic converters. According to experiment results, proposed 2-region logarithmic converter reduces 48.0% error range and 42.1% percent error. 21.6% area and 13.8% power consumption are gained.
A Low-Error, Cost-Efficient Design Procedure for Evaluating Logarithms to Be Used in a Logarithmic Arithmetic Processor
(2016-04)
Liu, Chih-Wei
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Ou, Shih-Hao
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Chang, Kuo-Chiang
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Lin, Tzung-Ching
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Chen, Shin-Kai
Based on an error-flattened, non-uniform-region linear-approximation algorithm, this brief proposes a low-error and a cost-efficient design procedure for realizing an optimized shift-and-add Logarithmic Unit (LU), which uses minimum hardware to meet the desired error constraint for embedded graphics systems. Mathematically, this brief first derives two solutions of the error-flattened algorithm. Subsequently, for an error constraint, the minimum number of approximation regions, n, the corresponding i th interpolation coefficients (a(i), b(i)), and the regional endpoints (x(i-1), x(i)), 1 <= i <= n, are obtained accordingly. Using the unique properties of the logarithmic function, spacing of x(i) is non-uniform to make errors in each region consistent. Carefully examining the cost of the applied add/sub network, a low-cost candidate for a shift-and-add LU is determined. Next, a cost exploration process, which gradually increases n, is performed. A large number of regions results in a more accurate conversion algorithm that might tolerate more implementation errors by using simple hardware whose cost is lower than that of the inferior candidate. After exploring the cost based on error tolerance, the proposed design procedure finally generates a hardware to meet the desired error constraint. Slightly modifying the regional endpoint x(i) increases hardware efficiency at the cost of increased error. Proposed circuits were synthesized in UMC 65RVT CMOS technology. Compared to state-of-the-art shift-and-add logarithmic converters, simulation results reveal that the proposed design saves approximately 12.7-51.1 percent area of polynomial approximation and improves approximately 1-14-dB SNR gain while achieving a tighter error constraint.
A Smart Stream Controller for Efficient Implementation of Streaming Applications on the Heterogeneous Multicore Processor
(2012)
Ou, Shih-Hao
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Yeh, Che-Wei
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Lin, Tai-Jyi
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Liu, Chih-Wei
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電子工程學系及電子研究所
Recently, many embedded systems adopt the heterogeneous multi-core processors, such as the TI OMAP and the IBM Cell BE, to allow offloading computation-intensive tasks from the MPU to the DSP for satisfying the increasing complexity of the emerging DSP streaming applications, such as the audio/video coding. By conventional parallel programming, task management is handled by the MPU with the OS or runtime assist. However, the thick OS stack or the laborious task management will significantly degrade the performance. This paper proposed a dedicated programmable smart stream controller, conforming to the streaming computation, to offload the task management from the MPU to greatly reduce runtime overhead. The smart stream controller provides a set of simple and high-level APIs to facilitate parallel programming on the heterogeneous multi-core processors. In our 512x512 JPEG encoding simulations, the proposed dedicated smart stream controller achieves up to 80% performance improvement compared to its software counterpart, i.e. implementing a runtime on MPU. Additionally, the performance scalability and capability of the smart stream controller to take advantage of architectural parallelism, adapting to varying number of DSP cores, are also presented.
A Systematic ANSI S1.11 Filter Bank Specification Relaxation and Its Efficient Multirate Architecture for Hearing-Aid Systems
(2016-08)
Yang, Cheng-Yen
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Liu, Chih-Wei
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Jou, Shyh-Jye
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
Recently, emerging mobile computing requires the high integration of hearing aids into a single system-on-chip. Modern hearing aid systems include a frequency decomposer, noise reduction, feedback cancellation, auditory compensation, and intelligent adaptation. The majority of existing works concentrated on improving the performance and efficiency on a single-signal processing block or one-sided effect. These works lacked comprehensive discussions on system-wide aspects regarding the overall impacts. To design an optimal hearing aid system, frequency decomposers, or the filter banks that dominate in hearing aid systems, are the first priority. We propose a systematic relaxation of the ANSI S1.11 specification and its design procedure for filter banks. The proposed design procedure overcomes the drawbacks of previous works and changes the five performance indices of the filter bank: delay, complexity, sub-band rate reduction, ripples of synthesized output, and prescription matching errors. These performance indices help system or algorithm designers in selecting a beneficial system-relaxed filter bank to achieve optimal hearing aids. The proposed multirate filter bank using the resampling method provides an efficient, low complexity, and delay-constrained computing architecture. Finally, seven design cases are used to demonstrate the proposed method, and comprehensive discussions of the five performance indices are presented.
A Variable-Latency, Ultra-Low-Voltage RISC Processor with a New In-Situ Error Detection and Correction Technique
(2016)
Lin, Chi-Chun
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Chang, Kuo-Chiang
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Liu, Chih-Wei
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
To overcome significant PVT variation in ultra low -voltage (LTV) operation, a new in-situ error detection and recovery mechanism is proposed to optimize circuit design for typical-case. The proposed technique detects glitch of a (ctitical-path) circuit output within the setup-time duration of a flip-flop and stalls the clock source, if possible, until the output is stable once an error is detected. Applying the proposed in-situ error detection, a test chip of an ULV 32-bit simple RISC with a 128-point FFT has been implemented with TSMC 40 nm CMOS process. The chip\'s measurement results confirms the functional correctness of the proposed in-situ error detection mechanism. Comparing that with the simple RISC with conventional worst case design principle, the proposed variable-latency ULV one reduces approximately 46% energy dissipation. And, with the similar energy consumption, the proposed PIN RISC achieves approximately 1.16 times throughput improvement.
A view of Gaussian elimination applied to early-stopped Berlekamp-Massey algorithm
(2007-06-01)
Liu, Chih-Wei
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Lu, Chung-Chin
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
In this paper, we adopt a restricted Gaussian elimination on the Hankel structured augmented syndrome matrix -to reinterpret an early-stopped version of the Berlekamp-Massey algorithm in which only (t + e) iterations are needed to be performed for the decoding of BCH codes up to t errors, where e is the number of errors actually occurred with e <= t, instead of the 2t iterations required in the conventional Berlekamp-Massey algorithm. The minimality of (t + e) iterations in this early-stopped Berlekamp-Massey (ESBM) algorithm is justified and related to the subject of simultaneous error correction and detection in this paper. We show that the multiplicative complexity of the ESBM algorithm is upper bounded by (te + e(2) - 1) for all e <= t and except for a trivial case, the ESBM algorithm is the most efficient algorithm for finding the error-locator polynomial.
AN EFFICIENT 18-BAND QUASI-ANSI 1/3-OCTAVE FILTER BANK USING RE-SAMPLING METHOD FOR DIGITAL HEARING AIDS
(2014-01-01)
Yang, Cheng-Yen
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Liu, Chih-Wei
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Jou, Shyh-Jye
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
This paper presents the multirate and re-sampling techniques to realize a low-delay, 18-band quasi-ANSI filter bank for digital hearing aids, which not only achieves a rather low computation complexity without a significant increase in the latency, but reduces greatly the total computation complexity for sub-band signal processing followed by the filter bank, such as noise reduction as well as wide dynamic range compression (WDRC). Researches done in the literature all focused on how to reduce the computation complexity of the filter bank. In particular, with the efficient multirate and interpolated FIR (IFIR) approaches for a 10-ms, 18-band quasi-ANSI filter bank, approximately 93% of the multiplications are saved, compared that with a straightforward parallel FIR filters architecture. However, they did not consider the computation complexity of the sub-band signal processing. In this paper, we first investigate realizing the FIR filter bank efficiently by using the multirate re-sampling techniques. To reduce the complexity, the optimized re-sampling factor for each filter band is explored carefully. Then, with the resampling technique, an efficient multirate quasi-ANSI FIR filter bank architecture is proposed. Compare to the state-of-the-art quasi-ANSI filter bank, approximately 17.7% of multiplicative complexity is reduced further and, up to 25% of the total computation complexity for sub-band signal processing followed by the filter bank is saved, but with only a slight increase in latency, i.e. 13.6 ms.
An energy-efficient, high-precision SFP LPFIR filter engine for digital hearing aids
(2015-01-01)
Ou, Shih-Hao
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Chang, Kuo-Chiang
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Liu, Chih-Wei
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
The main contribution of this study is the development of an area-/energy-efficient cascaded direct-truncation (DT) datapath with the so-called static floating-point (SFP) arithmetic to realize a low-delay analysis filter bank (AFB) for digital hearing aids. In the proposed SFP LPFIR (linear-phase finite impulse response) filter engine, lower silicon area and lesser power consumption facilitate better SNR performance than that achieved with the conventional post-truncation (PT) datapath with integer arithmetic. Moreover, in the proposed LPFIR filter engine, a cascaded 16-bit SFP A-M-S-Acc datapath is used that consists of two embedded 1-bit shifters to improve hardware usage and parallelism, one 16-bit DT adder (A), one 16-bit DT multiplier (M), one 16-bit barrel shifter (S), and one 16-bit DT accumulator (Acc). The operations per cycle (OPC) of the proposed SFP LPFIR filter engine reaches 6, which enables efficient fabrication of the low-latency AFB for hearing aids. To verify the effectiveness of the proposed 16-bit SFP LPFIR filter engine, a 10-ms 18-band quasi-ANSI S1.11 1/3-octave AFB for digital hearing aids was implemented using UMC 90-nm CMOS technology. The AFB was operated at 792 kHz to process, in real-time, 24 kHz audio, with the power consumption being approximately 80.6 mu W (at 1 V). Compared to the previous design in which the conventional PT datapath with integer arithmetic was used, approximately 9.6% of total power and 83% of silicon area were saved and almost the same SNR (signal-to-noise ratio) performance was achieved with the new system, when evaluated by a 3.96-s sequence of Mandarin speech. (C) 2014 Elsevier B.V. All rights reserved.
An Ultra-Low Voltage Hearing Aid Chip using Variable-Latency Design Technique
(2014-01-01)
Chang, Kuo-Chiang
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Luo, Shien-Chun
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Huang, Ching-Ji
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Liu, Chih-Wei
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Chu, Yuan-Hua
This paper presents a low-power hearing aid chip which operates under near-threshold voltage region to minimize energy consumption. The proposed variable-latency design technique compensates the performance degradation under ultra-low voltage, while the proposed FIR filter computing datapath improves the energy efficiency for filter bank computation in hearing aids. The hearing aid system composed of four heterogeneous processing elements to optimize the flexibility and power consumption. The overall system was fabricated in TSMC 65nm LP process. The measured results show that the power consumption achieves 500 mu W at 0.5V and 6 MHz.
Complexity-Aware Quantization and Lightweight VLSI Implementation of FIR Filters
(2011)
Kuo, Yu-Ting
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Lin, Tay-Jyi
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Liu, Chih-Wei
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
The coefficient values and number representations of digital FIR filters have significant impacts on the complexity of their VLSI realizations and thus on the system cost and performance. So, making a good tradeoff between implementation costs and quantization errors is essential for designing optimal FIR filters. This paper presents our complexity-aware quantization framework of FIR filters, which allows the explicit tradeoffs between the hardware complexity and quantization error to facilitate FIR filter design exploration. A new common subexpression sharing method and systematic bit-serialization are also proposed for lightweight VLSI implementations. In our experiments, the proposed framework saves 49% similar to 51% additions of the filters with 2's complement coefficients and 10% similar to 20% of those with conventional signed-digit representations for comparable quantization errors. Moreover, the bit-serialization can reduce 33% similar to 35% silicon area for less timing-critical applications.
Complexity-effective auditory compensation for digital hearing aids
(2008)
Kuo, Yu-Ting
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Lin, Tay-Jyi
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Chang, Wei-Han
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Li, Yueh-Tai
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Liu, Chih-Wei
This paper describes a complexity-effective design of auditory compensation, which is the most important building block in digital hearing aids. A multi-rate architecture and the filter bank design thereof are proposed to significantly reduce the data rates of the band-limited channels and thus the computational complexity. Several optimizations are discussed to further simplify the implementation of the dynamic range compressors in the multi-rate auditory compensation. In an 18-band 24-KHz digital hearing aid, 94% multiplications and additions are saved from a straightforward filter bank design. Moreover, the computation and memory requirements of the dynamic range compressor of each band are reduced to only 16% and 1% respectively.
Complexity-Effective Auditory Compensation with a Controllable Filter for Digital Hearing Aids
(2012)
Chang, Ya-Ting
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Chang, Kuo-Chiang
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Kuo, Yu-Ting
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Liu, Chih-Wei
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電子工程學系及電子研究所
Auditory compensation consumes significant power due to the computation-intensive operations in the filter bank. To reduce the complexity, a controllable filter was designed to replace the filter bank. Filter order was designed to match prescriptions within a specific error constraint with minimum computational cost. An interpolation scheme according to the variation of signal intensity was implemented to reduce the overhead of coefficients calculations. The proposed auditory compensation reduces 80% of multiplications and 30% of power consumption compared to the complexity-effective multi-rate filter bank architecture [4]. Moreover, the group delay was also reduced from 10 ms to 2.4 ms.
Complexity-Effective Dynamic Range Compression for Digital Hearing Aids
(2010)
Chang, Kuo-Chiang
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Kuo, Yu-Ting
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Lin, Tay-Jyi
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Liu, Chih-Wei
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電子工程學系及電子研究所
Dynamic range compression (DRC) is an essential function in digital hearing aids, which have stringent power consumption constraints. This work minimized the complexity of the DRC algorithm through adopting functional approximation for those involved nonlinear operations. The tradeoff between computation reduction and approximation error was explored for reducing hardware cost without introducing audible artifact. Moreover, finite wordlength analysis is conducted for the wordlength minimization and further complexity saving. The experimental result shows that our design totally reduces 96% computing complexity of the straightforward implementation without introducing audible difference in the output signals. Compared with other approximation methods, our design also requires lower hardware complexity.
Complexity-Effective Implementation of Programmable FIR Filters Using Simplified Canonic Signed Digit Multiplier
(2014-01-01)
Chang, Kuo-Chiang
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Lin, Ching-Hao
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Liu, Chih-Wei
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
This paper presents an energy-efficient FIR filter architecture which applies CSD multiplication to satisfy the design considerations of power consumption, flexibility and area cost. The proposed architecture reduces number of partial product rows and shift range of each coefficient multiplication to reduce energy consumption. However, the simplification restricts the use of filter coefficients. To mitigate this problem, this paper also presents a coefficient pre-processing flow to transform the original coefficients into applicable ones at design time to meet the restriction of the proposed multiplier. The simulation result reveals this technique can be applied for the computation of 97-tap filter. The design reduces up to 21.5% energy consumption per sample when compared with conventional Booth multiplier.
DeAr: A Framework for Power-efficient and Flexible Embedded Digital Signal Processor Design
(2016)
Lee, Chi-Ming
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Huang, Yong-Jyun
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Liu, Chih-Wei
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Hsu, Yarsun
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電子工程學系及電子研究所
The evolution of wireless communication protocols drives the quest of power-efficient and flexible computing for embedded DSPs, but popular architectures, very-long-instruction word (VLIW) and application-specific instruction set processor (ASIP), serve as opposite extreme cases in regard to power efficiency and flexibility. To this end, we present DeAr: Dual thread Architecture DSP, which manipulates a multi-banked register file that enables simultaneous multi-threading (SMT), and a transport-triggered bus that exploits the data forwarding mechanism in its compact datapath. We also propose a novel scheduling algorithm which leverages the compact hardware to achieve both high throughput and flexible computation. In the experiment of common DSP kernels, DeAr saves 20.3%43.1% and 31.8%-2.2% of power dissipation, 36.1%-31.5% and 28.2%5.7% of area, compared with VLIW and ASIP respectively.