Browsing by Author "Liu, Chun-Yi"

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A 3.52 Gb/s mmWave Baseband with Delayed Decision Feedback Sequence Estimation in 40 nm
(2015)
Preyss, Nicholas
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Senning, Christian
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Burg, Andreas
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Liu, Wei-Chang
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Liu, Chun-Yi
We present a digital baseband ASIC for 60 GHz single-carrier (SC) transmission that is optimized for communication scenarios in which most of the energy is concentrated in the first few channel taps. Such scenarios occur for example in office environments with strong reflections. Our circuit targets close-to-optimum maximum-likelihood performance under such conditions. To this end, we show for the first time how a reduced-state-sequence-estimation algorithm can be realized for the 1760 MHz bandwidth of the IEEE 802.11ad standard. The equalizer is complemented in the frontend by a synchronization unit for frequency offset compensation as well as a Golay-sequence based channel estimator and in the backend by an low density parity check (LDPC) decoder. In 40nm CMOS we achieve a measured data rate of up to 3.52 Gb/s using QPSK modulation.
A 802.15.3c/802.11ad Compliant 24 Gb/s FFT Processor for 60 GHz Communication Systems
(2015)
Davila, Henry Lopez
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Liu, Chun-Yi
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Liu, Wei-Chang
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Huang, Shen-Jui
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Jou, Shyh-Jye
This paper, we present a 24 Gb/s 512-point 8X-parallel FFT processor for 60 GHz communication systems. The proposed design is a pipelined Multipath Delay Feedback (MDF) radix-2(3) architecture, which exploits the parallelism of the multipath scheme together with pipeline technique to achieve a high throughput rate. Besides, the proposed FFT processor is implemented with an area efficient optimized multiplier architecture that avoid the need to store the twiddle factor in memory and a dynamic scaling technique to enhance the SQNR, allowing the FFT to operate with 16-QAM and 64-QAM for single carrier (SC) and orthogonal frequency-division multiplexing(OFDM) schemes. This FFT processor has been implemented in a SC/OFDM dual-mode baseband receiver satisfying the requirements of the 802.15.3c/802.11ad standard with a 40nm CMOS process. The post-layout implementation results show that the proposed FFT processor is able to achieve up to 24 Gb/s throughput rate at 500MHz clock with a power consumption of 87mW and area of 0.64mm(2).
A 802.15.3c/802.11ad Dual Mode Phase Noise Cancellation for 60 GHz Communication Systems
(2015)
Huang, Liang-Yu
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Wu, Chia-Yi
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Liu, Chun-Yi
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Liu, Wei-Chang
;
Wu, Chih-Feng
In this paper, a phase noise cancellation (PNC) architecture is presented for 60 GHz communication systems. The BER performance is severely degraded by the non-ideal carrier frequency in 60 GHz bandwidth, which causes both common phase error (CPE) and residual carrier frequency offset (RCFO). The proposed simplified two-stage CPE algorithm solves the RCFO and common phase nose in the frequency domain and eliminates the constellation rotation on each sub-channel. Two-stage architecture together with deep pipelining technique achieves a high throughput rate. This PNC architecture has been implemented in a SC/OFDM Dual-Mode baseband receiver satisfying the requirements of the 802.15.3c/802.11ad standard with a 40 nm process. The proposed PNC is able to support 64QAM/16QAM for OFDM/SC mode, and can achieve up to 19.2 Giga-hit per second (Gbps) throughput rate at 400 MHz operating frequency with power consumption of 33 mW and area of 0.142 mm(2).
A Memory Access Reordering Polyphase Network for 60 GHz FBMC-OQAM Baseband Receiver
(2016)
Liu, Chun-Yi
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Sie, Meng-Siou
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Leong, Edmund Wen Jen
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Yao, Yu-Cheng
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Jen, Chih-Wei
In this paper, a novel memory access reordering polyphase network (PPN) for 60 GHz filter bank multi-carrier (FBMC) offset QAM (OQAM) baseband receiver is presented. The 8X-parallelism architecture of PPN is integrated into our 8X-parallelism digital baseband receiver. The PPN is designed based on IEEE 802.15.3c and IEEE 802.11ad standards. The PPN contains three key modules including memory bank, filter coefficient selector and 4-tap PPN filter. The proposed PPN is synthesized with 40 nm 1P9M general purposes (GP) process. The implementation result shows it can operate at specified 330/500 MHz clock rate with power consumption of 17/26 mW at 0.81 V supply voltage. With 8X-parallelism architecture, the sampling rate supports up to 2.64/4 GHz.
A Millimeter Wave Digital CMOS Baseband Transceiver for Wireless LAN Applications
(2019-01-01)
Chiu, Kang-Lun
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Chan, Hsun-Wei
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Lee, Wei-Che
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Wu, Chang-Ting
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Lopez, Henry
In this paper, we introduce a 10 Gbps digital baseband transceiver with IV supply voltage, 16-QAM, 3/4 code rate single carrier mode using 28 nm CMOS process to do the implementation. In millimeter wave communications, well-defined standard, IEEE 802.11ad is referenced for our system design and simulation. We target at modified chip rate 2.5 GHz with 4 times parallelism hardware at clock rate 625 MHz. The overall transceiver architecture design with hardware implementation considerations will be proposed. With the smart shared memory allocation, we can reduce 31% of the total amount. According to the referenced specifications, we achieve the required bit error rate 3 x 10(-7) before SNR 18.5 dB. After the system algorithm design, we implement the hardware with the core area 2.92 mm(2) with measured power 1.8 Watt for baseband transceiver chip. The performance of energ,y per bit is 0.023 nJ and 0.211 nJ per hit 6w Tx and Rx, including ADC/DAC.
A MMSE Joint Feedback Feed-forward Equalizer for FBMC-OQAM Baseband Receiver in the 60 GHz Band
(2017-12-01)
Liu, Chun-Yi
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Leong, Edmund Wen Jen
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Wu, Chang-Ting
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Sie, Meng-Siou
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Lopez, Henry
In this paper, a minimum mean square error (MMSE) joint feedback feed-forward equalizer (MJFFE) is proposed to deterministically suppress the inter-symbol interference and inter-carrier interference that arose from the filter bank multi-carrier in a long multipath channel of the 60-GHz indoor wireless transmission. The decision device is discarded in the decision feedback loop to reduce error propagation while at the same time applying the MMSE criterion to prevent over compensation influenced by additive white Gaussian noise. As a result, in an non-line-of-sight (NLOS) channel with 7.65-ns rms delay spread, a 3-tap MJFFE provides 3-dB improvement at the bit error rate (BER) 10(-2) crossing and improve error floor effect at the BER 10(-3) crossing, as compared with the 1-tap zero-forcing equalizer. Furthermore, the proposed equalizer coefficients calculation based on linear convolution for the MJFFE is also presented. The hardware complexity achieves 50% reduction by using several methods including multiplexing, memory sharing, and computation element sharing.
A Pseudo MMSE Linear Equalizer for 60GHz Single Carrier Baseband Receiver
(2017-01-01)
Chan, Hsun-Wei
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Wu, Chang-Ting
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Jen, Chih-Wei
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Liu, Chun-Yi
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Lee, Wei-Che
In this paper, a pseudo minimum mean square error (P-MMSE) frequency domain equalizer (FDE) is proposed to combat deep fading channel for single carrier (SC) modulation under IEEE 802.11ad and IEEE 802.15.3c standard. This FDE has resistance like MMSE to deep fading channel and maintain low complexity like zero-forcing (ZF) equalizer. In order to calculate bit error rate (BER) performance, the proposed P-MMSE integrating with our previous dual-mode baseband receiver [1] to do simulation. P-MMSE FDE can provide about 1dB improvement for 16QAM and 5 dB improvement for QPSK and BPSK when BER at 10(-2) in serious deep fading channel. Besides, it enhances the BER floor from 4 x 10(-3) to 10(-3) in 16-QAM. Moreover, P-MMSE FDE maintains the same complexity as ZF FDE.
An 8X-Parallelism Memory Access Reordering Polyphase Network for 60 GHz FBMC-OQAM Baseband Receiver
(2016-12-01)
Liu, Chun-Yi
;
Sie, Meng-Siou
;
Leong, Edmund Wen Jen
;
Yao, Yu-Cheng
;
Lopez, Henry
Filter bank multi-carrier (FBMC) is a kind of new waveform that is an important topic in 5th generation wireless systems (5G). In this paper, we propose a novel memory access reordering polyphase network (PPN) for FBMC offset QAM (OQAM) system at 60 GHz band. The novel PPN architecture has lower complexity than the state-of-the-art designs, and it can be used in any FBMC-OQAM baseband design. To evaluate the system performance and hardware complexity of baseband receiver in millimeter wave (mmW) band, the proposed PPN is integrated into our 8X-parallelism 60 GHz band baseband receiver. The out-of-band (OOB) radiation in fixed-point simulation has 25 dB improvement as compared with OFDM. Furthermore, the transmission efficiency of FBMC-OQAM baseband receiver can improve 52% due to using more data subcarriers and removal of cyclic prefix (CP). The proposed PPN is synthesized with 40 nm 1P9M general purposes (GP) process, and can operate at 330/500 MHz clock rate with power consumption of 17/26 mW, providing the maximum PHY data rate up to 21.4 Gb/s.
An 8X-Parallelism Memory Access Reordering Polyphase Network for 60 GHz FBMC-OQAM Baseband Receiver
(2016-12)
Liu, Chun-Yi
;
Sie, Meng-Siou
;
Leong, Edmund Wen Jen
;
Yao, Yu-Cheng
;
Lopez, Henry
Filter bank multi-carrier (FBMC) is a kind of new waveform that is an important topic in 5th generation wireless systems (5G). In this paper, we propose a novel memory access reordering polyphase network (PPN) for FBMC offset QAM (OQAM) system at 60 GHz band. The novel PPN architecture has lower complexity than the state-of-the-art designs, and it can be used in any FBMC-OQAM baseband design. To evaluate the system performance and hardware complexity of baseband receiver in millimeter wave (mmW) band, the proposed PPN is integrated into our 8X-parallelism 60 GHz band baseband receiver. The out-of-band (OOB) radiation in fixed-point simulation has 25 dB improvement as compared with OFDM. Furthermore, the transmission efficiency of FBMC-OQAM baseband receiver can improve 52% due to using more data subcarriers and removal of cyclic prefix (CP). The proposed PPN is synthesized with 40 nm 1P9M general purposes (GP) process, and can operate at 330/500 MHz clock rate with power consumption of 17/26 mW, providing the maximum PHY data rate up to 21.4 Gb/s.
Digital Self-Interference Cancellation for OFDM Full-Duplex Transmission in 60 GHz Band
(2018-01-01)
Jen, Chih-Wei
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Yang, Hung-Wei
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Chan, Hsun-Wei
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Liu, Hung-Chih
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Lopez, Henry
In this paper, we proposed an all-digital selfinterference cancellation (DSIC) with correction vector for convolution (CVC) technique to eliminate serious multipath self-interference for orthogonal frequency-division multiplexing (OFDM) full-duplex transmission in 60 GHz band. The CVC can solve the non-equivalence of circular and linear convolution. This work based on IEEE 802.15.3c/IEEE 802.11ad specification is synthesized with 40 nm 1P9M general purposes process. Under the Access Point (AP) and the User Equipment (UE) horn antennas being aligned face to face, the 9-bit fixed-point simulation result shows the proposed technique can achieve the target of the uncoded bit-error-rate (BER) of 10-2 at signal-to-noise ratio (SNR) of 24.8 dB satisfying the requirement of 26 dB.
Dual-Mode All-Digital Baseband Receiver With a Feed-Forward and Shared-Memory Architecture for Dual-Standard Over 60 GHz NLOS Channel
(2017-03-01)
Liu, Chun-Yi
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Sie, Meng-Siou
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Leong, Edmund Wen Jen
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Yao, Yu-Cheng
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Jen, Chih-Wei
In this paper, an 8X-parallelism all-digital baseband receiver is proposed to support SC and OFDM modes for both IEEE 802.15.3c and IEEE 802.11ad standards. The all-digital baseband receiver contains a 4-in-1 synchronization (SYNC), a 512-point radix-23 IFFT/FFT, a phase noise cancellation (PNC), a shared memory (MEM) bank and a frequency-domain equalizer (FDE) with an optimized golay-correlator window-based noise cancellation (OGC-WNC) channel estimation (CE) for non-line-of-sight (NLOS) and line-of-sight (LOS) channels. The hardware sharing is 99% between SC and OFDM modes and the shared memory reduces memory usage by 51%. The measurement results show that the fabricated chip can provide PHY data rate of 9.24 Gb/s with power consumption of 497 mW to meet the requirement of OFDM mode for IEEE 802.15.3c and 802.11ad standards. Besides, the PHY data rate of the fabricated chip reaches 14 Gb/s with power consumption of 698 mW for OFDM mode that is beyond the standard requirement to offer higher PHY data rate over 60 GHz transmission environment.
Golay-Correlator Window-Based Noise Cancellation Equalization Technique for 60-GHz Wireless OFDM/SC Receiver
(2016-11)
Wu, Chih-Feng
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Liu, Wei-Chang
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Tsui, Chia-Chun
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Liu, Chun-Yi
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Sie, Meng-Siou
In this paper, a Golay-correlator window-based noise cancellation (GC-WNC) technique with frequency-domain equalizer (FDE) is proposed. The GC-WNC is a cooperative scheme in the time and frequency domains to combat the multipath effect in nonline-of-sight (NLOS) and LOS channels for orthogonal frequency-division multiplexing (OFDM) and single-carrier mode baseband inner receiver over 60-GHz environment for IEEE 802.15.3c and 802.11ad. According to mean-square error criterion, WNC approach is to minimize the estimation error between the ideal and the estimated channel frequency response (CFR) on each subchannel. The CFR is precisely obtained as coefficients of FDE to compensate multipath effect even in NLOS channel. The GC-WNC FDE with 8X-parallelism is designed as a part of digital baseband inner receiver with 40-nm CMOS general-purpose process. Because of area restriction of tape-out chip, only the OFDM mode is fabricated in the chip. The GC-WNC FDE has an equivalent gate count of 230k occupying 11.3% of the baseband inner receiver. Based on the chip measurement results, the baseband inner receiver with GC-WNC FDE provides 24-Gb/s throughput with 500-MHz operating clock and 0.94 V supply voltage. The power consumption of GC-WNC FDE is 69.79 mW. The baseband inner receiver with GC-WNC FDE can deliver a multigigabit per second throughput with the power dissipation of 2.91/2.26 mW/Gb/s at 500-/330-MHz operating clock for the OFDM mode.
Heterogeneous and Homogeneous Nucleation of Epitaxial NiSi(2) in [110] Si Nanowires
(2011-01-20)
Chou, Yi-Chia
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Wu, Wen-Wei
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Lee, Chung-Yang
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Liu, Chun-Yi
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Chen, Lih-Juann
We report here both heterogeneous and homogeneous nucleation of epitaxial suicide of NiSi(2) in Si nanowires grown in [110] direction by in situ observation in high-resolution transmission electron microscopy (TEM). Owing to the excellent lattice match between Si and NiSi(2), a giant epitaxial step of 2-8 nm wide forms at the interface between Si and NiSi(2) during the growth of the latter. The step formation results in two suicide/Si interfaces parallel to each other in TEM observations. Heterogeneous nucleation of NiSi(2) occurs at the intersection where the step meets the interfaces. However, we have also observed the epitaxial growth of NiSi(2) having a single interface with the Si, i.e., without a giant step. Homogeneous nucleation of NiSi(2) occurs on the single interface. Incubation time of heterogeneous nucleation of NiSi(2) has been measured by high-resolution video to be much shorter than that of homogeneous nucleation. The overall growth rate of NiSi(2) for the case of heterogeneous nucleation is faster than that for the case of homogeneous nucleation. Kinetic analysis of both types of nucleation is presented for a direct comparison in order to have a better understanding of the nucleation events.
Heterogeneous and Homogeneous Nucleation of Epitaxial NiSi2 in [110] Si Nanowires
(2011-01-20)
Chou, Yi-Chia
;
Wu, Wen-Wei
;
Lee, Chung-Yang
;
Liu, Chun-Yi
;
Chen, Lih-Juann
We report here both heterogeneous and homogeneous nucleation of epitaxial suicide of NiSi2 in Si nanowires grown in [110] direction by in situ observation in high-resolution transmission electron microscopy (TEM). Owing to the excellent lattice match between Si and NiSi2, a giant epitaxial step of 2-8 nm wide forms at the interface between Si and NiSi2 during the growth of the latter. The step formation results in two suicide/Si interfaces parallel to each other in TEM observations. Heterogeneous nucleation of NiSi2 occurs at the intersection where the step meets the interfaces. However, we have also observed the epitaxial growth of NiSi2 having a single interface with the Si, i.e., without a giant step. Homogeneous nucleation of NiSi2 occurs on the single interface. Incubation time of heterogeneous nucleation of NiSi2 has been measured by high-resolution video to be much shorter than that of homogeneous nucleation. The overall growth rate of NiSi2 for the case of heterogeneous nucleation is faster than that for the case of homogeneous nucleation. Kinetic analysis of both types of nucleation is presented for a direct comparison in order to have a better understanding of the nucleation events.
Interference Measurement and Analysis of Full-Duplex Wireless System in 60 GHz Band
(2016)
Yang, Hung-Wei
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He, Yongyu
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Jen, Chih-Wei
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Liu, Chun-Yi
;
Jou, Shyh-Jye
With co-time co-frequency full duplex (CCFD) in 60 GHz band, self interference (SI) has different characteristics due to larger wireless path loss and beamformed system compared to current band under 6 GHz (normal band). In this paper, we present real SI channel measurement results and analysis to consider indoor CCFD in 60 GHz band. The results show that the narrow beam antennas can effectively suppress the direct leakage component but increase the root mean square (HMS) delay spread of the SI channel due to reflections from nearby objects. The effect of phase noise on SI cancellation is demonstrated since a high-frequency oscillator is used. At the end, we show the key factors of SI cancellation based on the measurement results for implementation of CCFD in 60 GHz band.
Residual Sampling Clocking Offset Estimation and Compensation for FBMC-OQAM Baseband Receiver in the 60 GHz Band
(2017-01-01)
Liu, Chun-Yi
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Yao, Yu-Cheng
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Sie, Meng-Siou
;
Leong, Edmund Wen Jen
;
Lopez, Henry
In this paper, we propose a tracking mechanism for the residual sampling clocking offset (SCO) with corresponding pilot and auxiliary pilot arrangements for filter bank multi-carrier (FBMC) offset QAM (OQAM) baseband receiver in the 60 GHz band. This work can effectively compensate the non-ideal effects on the high-band subcarriers while using more data subcarrier for increasing bandwidth efficiency. This work is designed based on IEEE 802.15.3c and IEEE 802.11ad standards and synthesized with 40 nm 1P9M general purposes (GP) process. The proposed SCO tracking module with the proposed alternated pilot and auxiliary pilot arrangement can improve the BER floor and reach to 10(-2) at SNR of 22 dB which is only 1.75 dB more than that of no SCO effect in 64-QAM modulation.