Browsing by Author "Liu, FM"

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3D monochromatic image synthesized with vertical area-partitioned recording of master hologram in multiple-exposure holography
(2001-08-01)
Zhai, HC
;
Mu, GG
;
Wang, MW
;
Liu, FM
;
Pan, D
We report for the first time theoretical analysis and experimental results of a vertical-area partition method for recording master holograms in multiple-exposure rainbow holography to synthesize monochromatic 3D image from a series of medical tomograms. In this novel method, the master hologram is area partitioned into elementary master holograms, which are recorded in a periodic arrangement along the vertical direction. Under the white-light reconstruction, a 3D monochromatic image composed of a series of medical tomograms can be synthesized with wide viewing angle, high resolution, and low color blur. (C) 2001 Published by Elsevier Science B.V.
Low-temperature and low thermal budget fabrication of polycrystalline silicon thin-film transistors
(1996-11-01)
Lin, HY
;
Chang, CY
;
Lei, TF
;
Liu, FM
;
Yang, WL
A top-gate self-aligned n-channel polycrystalline silicon (poly-Si) thin-film transistor (TFT) has been fabricated with low temperature (less than or equal to 550 degrees C) and low thermal budget process. The ultrahigh vacuum chemical vapor deposition (UHV/CVD) grown poly-Si was served as the channel film, the chemical mechanical polishing (CMP) technique was used to polish the channel surface, plasma-enhanced chemical vapor deposited (PECVD) tetraethylorthosilicate (TEOS) oxide was used as the gate dielectric, and NH3 plasma was used to passive the device. In this process, the solid phase crystallization (SPC) step Is not needed. A field effect mobility of 46 cm(2)/V-s, ON/OFF current ratio of over 10(7), and threshold voltage of 0.8 V are obtained. The significant reduction in process temperature and thermal budget make this process advantageous for larger-area-display peripheral driver circuits on glass substrate.
Low-temperature and low thermal budget fabrication of polycrystalline silicon thin-film transistors
(1996-11-01)
Lin, HY
;
Chang, CY
;
Lei, TF
;
Liu, FM
;
Yang, WL
A top-gate self-aligned n-channel polycrystalline silicon (poly-Si) thin-film transistor (TFT) has been fabricated with low temperature (less than or equal to 550 degrees C) and low thermal budget process. The ultrahigh vacuum chemical vapor deposition (UHV/CVD) grown poly-Si was served as the channel film, the chemical mechanical polishing (CMP) technique was used to polish the channel surface, plasma-enhanced chemical vapor deposited (PECVD) tetraethylorthosilicate (TEOS) oxide was used as the gate dielectric, and NH3 plasma was used to passive the device. In this process, the solid phase crystallization (SPC) step Is not needed. A field effect mobility of 46 cm(2)/V-s, ON/OFF current ratio of over 10(7), and threshold voltage of 0.8 V are obtained. The significant reduction in process temperature and thermal budget make this process advantageous for larger-area-display peripheral driver circuits on glass substrate.
Viewing effects of 3-D images synthesized from a series of 2-D tomograms by VAP and HAP approaches
(2002)
Zhai, HC
;
Wang, MW
;
Liu, FM
;
Hsu, KY
;
光電工程學系
We report, for the first time, the experimental result and its analysis of synthesizing a series of simulating 2-D tomograms into a 3-D monochromatic image. Our result shows clearly the advantage in monochromaticity of a vertical area-partition (VAP) approach over a horizontal area-partition (HAP) approach during the final white-light reconstruction. This monochromaticity will ensure a 3-D image synthesis without any distortion in gray level or positional recovery.